View MC68EC000_2881825.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

motorola, 1995 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "typical" parameters can and do vary in different applications. all operating parameters, including "typicals" must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. ec000 core processor (scm68000) user? manual f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola ec000 core processor user? manual iii 68k fax-it documentation comments fax 512-891-8593?ocumentation comments only the motorola high-performance embedded systems technical communications depart- ment provides a fax number for you to submit any questions or comments about this docu- ment or how to order other documents. we welcome your suggestions for improving our documentation. please do not fax technical questions. please provide the part number and revision number (located in upper right-hand corner of the cover) and the title of the document. when referring to items in the manual, please ref- erence by the page number, paragraph number, figure number, table number, and line num- ber if needed. when sending a fax, please provide your name, company, fax number, and phone number including area code. applications and technical information for questions or comments pertaining to technical information, questions, and applications, please contact one of the following sales offices nearest you. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
iv ec000 core processor user? manual motorola ?sales offices field applications engineering available through all sales offices united states alabama , huntsville (205) 464-6800 arizona , tempe (602) 897-5056 california , agoura hills (818) 706-1929 california , los angeles (310) 417-8848 california , irvine (714) 753-7360 california , rosevllle (916) 922-7152 california , san diego (619) 541-2163 california , sunnyvale (408) 749-0510 colorado , colorado springs (719) 599-7497 colorado , denver (303) 337-3434 connecticut , wallingford (203) 949-4100 florida , maitland (407) 628-2636 florida , pompano beach/ fort lauderdale (305) 486-9776 florida , clearwater (813) 538-7750 georgla , atlanta (404) 729-7100 idaho , boise (208) 323-9413 illinois , chicago/hoffman estates (708) 490-9500 indlana , fort wayne (219) 436-5818 indiana , indianapolis (317) 571-0400 indiana , kokomo (317) 457-6634 iowa , cedar rapids (319) 373-1328 kansas , kansas city/mission (913) 451-8555 maryland , columbia (410) 381-1570 massachusetts , marborough (508) 481-8100 massachusetts , woburn (617) 932-9700 michigan , detroit (313) 347-6800 minnesota , minnetonka (612) 932-1500 missouri , st. louis (314) 275-7380 new jersey , fairfield (201) 808-2400 new york , fairport (716) 425-4000 new york , hauppauge (516) 361-7000 new york , poughkeepsie/fishkill (914) 473-8102 north carolina , raleigh (919) 870-4355 ohio , cleveland (216) 349-3100 ohio , columbus/worthington (614) 431-8492 ohio , dayton (513) 495-6800 oklahoma , tulsa (800) 544-9496 oregon , portland (503) 641-3681 pennsylvania , colmar (215) 997-1020 philadelphia/horsham (215) 957-4100 tennessee , knoxville (615) 690-5593 texas , austin (512) 873-2000 texas , houston (800) 343-2692 texas , plano (214) 516-5100 virginia , richmond (804) 285-2100 washington , bellevue (206) 454-4160 seattle access (206) 622-9960 wisconsin , milwaukee/brookfield (414) 792-0122 canada british columbia , vancouver (604) 293-7605 ontario , toronto (416) 497-8181 ontario , ottawa (613) 226-3491 quebec , montreal (514) 731-6881 international australia , melbourne (61-3)887-0711 australia , sydney (61(2)906-3855 brazil , sao paulo 55(11)815-4200 china , beijing 86 505-2180 finland , helsinki 358-0-35161191 car phone 358(49)211501 france , paris/vanves 33(1)40 955 900 germany , langenhagen/ hanover 49(511)789911 germany , munich 49 89 92103-0 germany , nuremberg 49 911 64-3044 germany , sindelfingen 49 7031 69 910 germany , wiesbaden 49 611 761921 hong kong , kwai fong 852-4808333 tai po 852-6668333 india , bangalore (91-812)627094 israel , tel aviv 972(3)753-8222 italy , milan 39(2)82201 japan , aizu 81(241)272231 japan , atsugi 81(0462)23-0761 japan , kumagaya 81(0485)26-2600 japan , kyushu 81(092)771-4212 japan , mito 81(0292)26-2340 japan , nagoya 81(052)232-1621 japan , osaka 81(06)305-1801 japan, sendai 81(22)268-4333 japan, tachikawa 81(0425)23-6700 japan, tokyo 81(03)3440-3311 japan , yokohama 81(045)472-2751 korea , pusan 82(51)4635-035 korea , seoul 82(2)554-5188 malaysia , penang 60(4)374514 mexico , mexico city 52(5)282-2864 mexico , guadalajara 52(36)21-8977 marketing 52(36)21-9023 customer service 52(36)669-9160 netherlands , best (31)49988 612 11 puerto rico , san juan (809)793-2170 singapore (65)2945438 spain , madrid 34(1)457-8204 or 34(1)457-8254 sweden , solna 46(8)734-8800 switzerland , geneva 41(22)7991111 switzerland , zurich 41(1)730 4074 talwan , taipei 886(2)717-7089 thailand , bangkok (66-2)254-4910 united kingdom , aylesbury 44(296)395-252 full line representatives colorado , grand junction cheryl lee whltely (303) 243-9658 kansas , wichita melinda shores/kelly greiving (316) 838 0190 nevada , reno galena technology group (702) 746 0642 new mexico , albuquerque s&s technologies, lnc. (505) 298-7177 utah , salt lake city utah component sales, inc. (801) 561-5099 washington , spokane doug kenley (509) 924-2322 argentina , buenos aires argonics, s.a. (541) 343-1787 hybrid components resellers elmo semiconductor (818) 768-7400 minco technology labs inc. (512) 834-2022 semi dice inc. (310) 594-4631 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola ec000 core processor user? manual v preface the ec000 core processor user's manual describes the programming, capabilities, and operation of the scm68000 (ec000 core); the mc68000 family programmer? reference manual provides instruction details for the ec000 core; and the flexcore product brief pro- vides a brief description of the flexcore program. the organization of this manual is as follows: section 1 overview section 2 signal description section 3 bus operation section 4 exception processing section 5 8-bit instruction execution times section 6 16-bit instruction execution times section 7 electrical characteristics trademarks composer, verilog, verifault, and veritime are trademarks of cadence design sys- tems, inc. synopsys is a registered trademark of synopsys, inc. tds is a registered trademark of summit design, inc. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
vi ec000 core processor user? manual motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola ec000 core processor user? manual vii table of contents section 1 overview 1.1 flexcore integrated processors ................................................................... 1-2 1.1.1 flexcore advantages ................................................................................. 1-4 1.1.2 flexcore module types.............................................................................. 1-4 1.2 development cycle....................................................................................... 1-5 1.3 programming model...................................................................................... 1-7 1.4 data types and addressing modes.............................................................. 1-9 1.5 data organization ....................................................................................... 1-10 1.5.1 data registers .......................................................................................... 1-10 1.5.2 address registers .................................................................................... 1-10 1.5.3 data organization in memory................................................................... 1-10 1.6 instruction set summary............................................................................. 1-11 section 2 signal description 2.1 address bus (a31?0) ................................................................................. 2-1 2.2 data bus (d15?0)....................................................................................... 2-1 2.3 clock (clki, clko)...................................................................................... 2-1 2.4 asynchronous bus control ........................................................................... 2-3 2.4.1 address strobe (asb) ................................................................................ 2-3 2.4.2 read/write (rwb) and early read/write (erwb)..................................... 2-3 2.4.3 upper and lower data strobes (udsb, ldsb), and data strobe (dsb) .. 2-4 2.4.4 data transfer acknowledge (dtackb) ..................................................... 2-4 2.4.5 data transfer size (siz1?iz0) ................................................................. 2-4 2.4.6 read-modify-write (rmcb) ........................................................................ 2-5 2.5 bus arbitration control.................................................................................. 2-5 2.5.1 bus request (brb) .................................................................................... 2-5 2.5.2 bus grant (bgb)......................................................................................... 2-5 2.5.3 bus grant acknowledge (bgackb)?-wire protocol only ...................... 2-5 2.6 interrupt control (iplb2?plb0) ................................................................... 2-5 2.7 system control ............................................................................................. 2-6 2.7.1 bus error (berrb)..................................................................................... 2-6 2.7.2 reset external/internal (resetib, resetob) ......................................... 2-6 2.7.3 halt external/internal (haltib, haltob).................................................. 2-6 2.7.4 mode (mode)............................................................................................. 2-7 2.7.5 disable control (disb) ............................................................................... 2-7 2.7.6 test mode (test) ...................................................................................... 2-7 2.7.7 test clock (testclk) ............................................................................... 2-7 2.7.8 autovector (avecb) ................................................................................... 2-8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
table of contents viii ec000 core processor user? manual motorola 2.8 three-state control ...................................................................................... 2-8 2.8.1 address output enable (aoeb) ................................................................. 2-8 2.8.2 control output enable (coeb) .................................................................. 2-8 2.8.3 data output enable (doeb) ...................................................................... 2-8 2.9 processor status .......................................................................................... 2-8 2.9.1 function codes (fc2?c0) ....................................................................... 2-8 2.9.2 address three-state control (tscae) ...................................................... 2-9 2.9.3 stop instruction indicator (stop)............................................................... 2-9 2.9.4 interrupt pending (ipendb) ....................................................................... 2-9 2.9.5 cpu pipe refill (refillb)......................................................................... 2-9 2.9.6 microsequencer status indication (statusb) .......................................... 2-9 2.10 multiplexing pins........................................................................................... 2-9 section 3 bus operation 3.1 data transfer operations ............................................................................. 3-1 3.1.1 read cycle ................................................................................................. 3-2 3.1.2 write cycle ................................................................................................. 3-8 3.1.3 read-modify-write cycle.......................................................................... 3-13 3.2 bus arbitration ............................................................................................ 3-17 3.2.1 requesting the bus .................................................................................. 3-18 3.2.2 receiving the bus grant........................................................................... 3-18 3.2.3 acknowledgment of mastership (3-wire bus arbitration only)................. 3-19 3.3 bus arbitration control................................................................................ 3-22 3.4 bus error and halt operation ..................................................................... 3-30 3.4.1 bus error operation.................................................................................. 3-30 3.4.2 retrying the bus cycle ............................................................................. 3-32 3.4.3 halt operation .......................................................................................... 3-32 3.4.4 double bus fault ...................................................................................... 3-35 3.5 asynchronous operation ............................................................................ 3-35 3.6 synchronous operation .............................................................................. 3-38 3.7 the relationship of dtackb, berrb, and haltib ................................. 3-42 section 4 exception processing 4.1 privilege modes ............................................................................................ 4-1 4.1.1 supervisor mode ........................................................................................ 4-2 4.1.2 user mode .................................................................................................. 4-2 4.1.3 privilege mode changes ............................................................................ 4-2 4.1.4 reference classification............................................................................. 4-3 4.1.5 cpu space cycle....................................................................................... 4-3 4.1.5.1 interrupt acknowledge cycle.................................................................... 4-3 4.1.5.2 autovectored interrupt acknowledge cycle ............................................. 4-7 4.2 exception processing description .............................................................. 4-11 4.2.1 exception vectors..................................................................................... 4-11 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
table of contents motorola ec000 core processor user? manual ix 4.2.2 kinds of exceptions .................................................................................. 4-13 4.2.3 multiple exceptions................................................................................... 4-13 4.2.4 exception stack frames........................................................................... 4-14 4.2.5 exception processing sequence .............................................................. 4-14 4.3 processing of specific exceptions .............................................................. 4-15 4.3.1 reset ........................................................................................................ 4-15 4.3.1.1 reset operation ..................................................................................... 4-16 4.3.1.1.1 reset using resetib and haltib ..................................................... 4-16 4.3.1.1.2 reset instruction................................................................................... 4-16 4.3.1.1.3 reset using only resetib ................................................................. 4-17 4.3.1.2 initializing the scm68000 for simulation ................................................ 4-18 4.3.2 interrupts................................................................................................... 4-19 4.3.2.1 level seven interrupts............................................................................ 4-20 4.3.2.2 uninitialized interrupt .............................................................................. 4-20 4.3.2.3 spurious interrupt ................................................................................... 4-20 4.3.3 instruction traps ....................................................................................... 4-21 4.3.4 illegal and unimplemented instructions .................................................... 4-21 4.3.5 privilege violations ................................................................................... 4-21 4.3.6 tracing...................................................................................................... 4-22 4.3.7 bus error................................................................................................... 4-22 4.3.8 address error............................................................................................ 4-23 section 5 8-bit instruction execution times 5.1 operand effective address calculation times ............................................. 5-1 5.2 move instruction execution times .............................................................. 5-2 5.3 standard instruction execution times .......................................................... 5-3 5.4 immediate instruction execution times ........................................................ 5-4 5.5 single operand instruction execution times................................................ 5-5 5.6 shift/rotate instruction execution times ...................................................... 5-6 5.7 bit manipulation instruction execution timess ............................................. 5-6 5.8 conditional instruction execution times....................................................... 5-6 5.9 jmp, jsr, lea, pea, and movem instruction execution times ................ 5-7 5.10 multiprecision instruction execution times................................................... 5-7 5.11 miscellaneaous instruction execution times ................................................ 5-8 5.12 exception processing execution times........................................................ 5-9 section 6 16-bit instruction execution times 6.1 operand effective address calculation times ............................................. 6-1 6.2 move instruction execution times .............................................................. 6-2 6.3 standard instruction execution times .......................................................... 6-3 6.4 immediate instruction execution times ........................................................ 6-4 6.5 single operand instruction execution times................................................ 6-5 6.6 shift/rotate instruction execution times ...................................................... 6-6 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
table of contents x ec000 core processor user? manual motorola 6.7 bit manipulation instruction execution times ............................................... 6-6 6.8 conditional instruction execution times....................................................... 6-7 6.9 jmp, jsr, lea, pea, and movem instruction execution times ................ 6-7 6.10 multiprecision instruction execution times................................................... 6-7 6.11 miscellaneous instruction execution times.................................................. 6-8 6.12 exception processing execution times........................................................ 6-9 section 7 electrical characteristics 7.1 maximum ratings ......................................................................................... 7-1 7.2 cmos considerations .................................................................................. 7-1 7.3 power consumption ..................................................................................... 7-1 7.4 ac electrical specification definitions .......................................................... 7-1 7.5 ac electrical specifications?lock timing.................................................. 7-2 7.6 ac electrical specifications?ead and write cycles.................................. 7-2 7.7 ac electrical specifications?cm68000 to external peripherals ............... 7-6 7.8 ac electrical specifications?us arbitration............................................... 7-7 7.9 ac electrical specifications?ore applications signals ........................... 7-11 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola ec000 core processor user? manual xi list of illustrations 1-1 flexcore integrated processor typical die layout............................................ 1-3 1-2 standard cell design flow................................................................................. 1-6 1-3 programming model ........................................................................................... 1-7 1-4 status register................................................................................................... 1-8 1-5 word organization in memory.......................................................................... 1-10 1-6 data organization in memory........................................................................... 1-12 2-1 input/output signals........................................................................................... 2-2 3-1 word read cycle flowchart for 16-bit mode ..................................................... 3-2 3-2 byte read cycle flowchart for 8-bit mode ........................................................ 3-3 3-3 byte read cycle flowchart for 16-bit mode ...................................................... 3-3 3-4 read and write cycle timing diagram for 8-bit mode ...................................... 3-4 3-5 read and write cycle timing diagram for 16-bit mode .................................... 3-5 3-6 word and byte read cycle timing diagram for 16-bit mode ............................ 3-6 3-7 word write cycle flowchart for 16-bit mode ..................................................... 3-8 3-8 byte write cycle flowchart for 8-bit mode......................................................... 3-9 3-9 byte write cycle flowchart for 16-bit mode....................................................... 3-9 3-10 write cycle timing diagram for 8-bit mode ..................................................... 3-10 3-11 word and byte write cycle timing diagram for 16-bit mode .......................... 3-11 3-12 read-modify-write cycle flowchart................................................................. 3-13 3-13 read-modify-write cycle timing diagram ....................................................... 3-14 3-14 3-wire bus arbitration cycle flowchart............................................................ 3-18 3-15 2-wire bus arbitration cycle flowchart............................................................ 3-19 3-16 3-wire bus arbitration timing diagram............................................................ 3-20 3-17 2-wire bus arbitration timing diagram............................................................ 3-21 3-18 bus arbitration unit state diagrams................................................................. 3-23 3-19 3-wire bus arbitration timing diagram?cm68000 active ........................... 3-24 3-20 3-wire bus arbitration timing diagram?us inactive..................................... 3-25 3-21 3-wire bus arbitration timing diagram?pecial case ................................... 3-26 3-22 2-wire bus arbitration timing diagram?cm68000 active ........................... 3-27 3-23 2-wire bus arbitration timing diagram?us inactive..................................... 3-28 3-24 2-wire bus arbitration timing diagram?pecial case ................................... 3-29 3-25 bus error timing diagram................................................................................ 3-31 3-26 retry bus cycle timing diagram ..................................................................... 3-33 3-27 halt operation timing diagram........................................................................ 3-34 3-28 external asynchronous signal synchronization............................................... 3-35 3-29 fully asynchronous read cycle ...................................................................... 3-36 3-30 fully asynchronous write cycle....................................................................... 3-36 3-31 pseudo-asynchronous read cycle.................................................................. 3-37 3-32 pseudo-asynchronous write cycle.................................................................. 3-38 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
list of illustrations xii ec000 core processor user? manual motorola 3-33 synchronous read cycle................................................................................. 3-39 3-34 synchronous write cycle................................................................................. 3-40 4-1 cpu space address encoding .......................................................................... 4-3 4-2 interrupt acknowledge cycle timing diagram ................................................... 4-4 4-3 autovector operation timing diagram............................................................... 4-8 4-4 autovector operation timing diagram?est case........................................... 4-9 4-5 autovector operation timing diagram?orst case ...................................... 4-10 4-6 exception vector format.................................................................................. 4-11 4-7 address translated from 8-bit vector number ................................................ 4-11 4-8 interrupt vector number format ...................................................................... 4-13 4-9 groups 1 and 2 exception stack frame .......................................................... 4-15 4-10 reset circuit..................................................................................................... 4-16 4-11 reset operation timing diagram..................................................................... 4-17 4-12 resetob timing diagram.............................................................................. 4-18 4-13 initialization of the scm68000 for simulation timing diagram ........................ 4-19 4-14 supervisor stack order for bus or address error exception ........................... 4-23 7-1 clock input timing diagram............................................................................... 7-2 7-2 read cycle timing diagram .............................................................................. 7-4 7-3 write cycle timing diagram .............................................................................. 7-5 7-4 scm68000 to external peripherals timing diagram ......................................... 7-6 7-5 bus arbitration timing diagram ......................................................................... 7-7 7-6 bus arbitration timing diagram?dle bus case ............................................... 7-8 7-7 bus arbitration timing diagram?ctive bus case ........................................... 7-9 7-8 bus arbitration timing diagram?ultiple bus request.................................. 7-10 7-9 core application signals timing diagram........................................................ 7-12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola ec000 core processor user? manual xiii list of tables 1-1 data addressing modes ..................................................................................... 1-9 1-2 notational conventions .................................................................................... 1-13 1-3 instruction set summary .................................................................................. 1-14 2-1 signal summary ................................................................................................. 2-2 2-2 upper and lower data strobe control of data bus ........................................... 2-4 2-3 lower data strobe control of data bus ............................................................. 2-4 2-4 data transfer size ............................................................................................. 2-5 2-5 interrupt levels and mask values ...................................................................... 2-6 2-6 function code outputs ...................................................................................... 2-8 2-7 status indication exceptions .............................................................................. 2-9 2-8 pin multiplexing priority .................................................................................... 2-10 3-1 dtackb, berrb, and haltib assertion results.......................................... 3-43 3-2 berrb and haltib negation results ............................................................ 3-44 4-1 reference classification..................................................................................... 4-3 4-2 exception vector assignment .......................................................................... 4-12 4-3 exception grouping and priority....................................................................... 4-14 5-1 effective address calculation times.................................................................. 5-2 5-2 move byte instruction execution times ............................................................. 5-2 5-3 move word instruction execution times............................................................ 5-3 5-4 move long instruction execution times ............................................................ 5-3 5-5 standard instruction execution times................................................................ 5-4 5-6 immediate instruction execution times ............................................................. 5-5 5-7 single operand instruction execution times ..................................................... 5-5 5-8 shift/rotate instruction execution times ........................................................... 5-6 5-9 bit manipulation instruction execution times..................................................... 5-6 5-10 conditional instruction execution times ............................................................ 5-7 5-11 jmp, jsr, lea, pea, and movem instruction execution times...................... 5-7 5-12 multiprecision instruction execution times ........................................................ 5-8 5-13 miscellaneous instruction execution times ....................................................... 5-8 5-14 move peripheral instruction execution times .................................................... 5-9 5-15 exception processing execution times ............................................................. 5-9 6-1 effective address calculation times.................................................................. 6-2 6-2 move byte and word instruction execution times............................................. 6-2 6-3 move long instruction execution times ............................................................ 6-3 6-4 standard instruction execution times................................................................ 6-4 6-5 immediate instruction execution times ............................................................. 6-5 6-6 single operand instruction execution times ..................................................... 6-5 6-7 shift/rotate instruction execution times ........................................................... 6-6 6-8 bit manipulation instruction execution times..................................................... 6-6 6-9 conditional instruction execution times ............................................................ 6-7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
list of tables xiv ec000 core processor user? manual motorola 6-10 jmp, jsr, lea, pea, and movem instruction execution times ..................... 6-7 6-11 multiprecision instruction execution times ........................................................ 6-8 6-12 miscellaneous instruction execution times ....................................................... 6-8 6-13 move peripheral instruction execution times.................................................... 6-9 6-14 exception processing execution times ............................................................. 6-9 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola ec000 core processor user? manual 1-1 section 1 overview this document contains a summary of the use and operation of the scm68000 micropro- cessor core (also referred to as the ec000 core) 1 and a detailed set of timing and electrical specifications. refer to the m68000 8-/16-/32-bit microprocessor user? manual (m68000um/ad) for detailed information on the operation of the instruction set, addressing modes, and bus architecture for this core. the scm68000 is a core implementation of the mc68000 32-bit microprocessor and is designed to be used as part of the flexcore program. in the flexcore program, high-volume manufacturers can create their own integrated microprocessor containing a core processor, such as the scm68000, and their own proprietary technology. a flexcore integrated pro- cessor allows significant reductions in component count, power consumption, board space, and cost while yielding much higher system reliability and performance. the main features of the scm68000 include: low-power hcmos implementation requires only 15 ma at 3.3 v 32-bit performance for 16-bit applications?.7 mips at 16 mhz statically selectable 8-bit or 16-bit data bus operation 32-bit address bus directly addresses up to 4 gbytes of address space static operation provides almost zero power consumption during idle periods sixteen general-purpose 32-bit data and address registers fifty-six powerful instruction types that support high-level programming languages fourteen addressing modes and five main data types allow compact, efficient code seven priority level interrupt control special core interfacing signals emulation support signals including pipeline refill, processor status, and interrupt pending signals both 3.3-v and 5-v operation the scm68000 has a statically selectable 8-bit or 16-bit data bus. the address bus is 32- bits wide and may be used as either a 24-bit address bus as on the mc68000 microproces- sors, or as a 32-bit address bus to fully support the internal architecture. the 32-bit address 1. the scm68000 is the name of the verilog model for the ec000 core. the remainder of this section will refer to the ec000 core as only the scm68000. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview 1-2 ec000 core processor user? manual motorola bus allows direct addressing of up to 4 gbytes. logic can be added to implement dynamic bus sizing. the scm68000 is upward code compatible with all other members of the m68000 micropro- cessor family. any user-mode programs using the scm68000 instruction set will run unchanged on any mc680x0, mc68ec0x0, or mc683xx processor. this is possible because the user programming model is identical for all processors and the instruction sets, addressing modes, and data types for the scm68000 are proper subsets of the complete architecture. the scm68000 also includes some functions not found on the standard mc68000 and MC68EC000 microprocessors such as the processor status, pipeline refill, and interrupt pending signals. these signals permit emulation support and facilitate interfacing between the scm68000 and on-chip logic. 1.1 flexcore integrated processors flexcore allows designers of high-volume digital systems and third-party technology provid- ers to place their proprietary circuitry on chip with a motorola microprocessor. by using flex- core, a designer can reduce the total system cost, component count, and power consumption while providing higher performance and greater reliability. up to 100,000 gates or more of custom logic, memory, and peripheral modules can be added to a core processor to produce the most cost-effective solution for a designer's system. the core processors provide special power-management features such as 5 v, 3.3 v, and static operation. the 68000 family of core processors offers the designer a range of performance from 3 to 12 million instructions per second (mips) (to be extended to 100 mips) while maintaining com- plete code compatibility throughout the family. the 68000 processors have a proven archi- tecture with a broad base of application and system software support, including real-time kernels, operating systems, and compilers, in addition to a wide range of tools to support software development. in the future, additional processing architectures will be included in the flexcore program, including powerpc and digital signal processing (dsp). figure 1- 1 shows a typical die layout for a flexcore integrated processor. complete product lines can be created using flexcore by implementing one base design using a variety of core processors. designers already familiar with 68000 family design can easily migrate to flexcore processors as the core processors use the same bus interfaces found on the standard 68000 family members. additionally, many peripheral modules and memory elements are available for integration. motorola has developed a complete design system to put into the hands of the customer that includes both a broad cell-based library and effective computer-aided design (cad) tools. by building on motorola's proven 68000 microprocessor architecture and superior manufacturing capabilities, flexcore offers designers the best path to higher system integration. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview motorola ec000 core processor user? manual 1-3 flexcore custom processors are ideal for: high-volume users of 8-, 16-, and 32-bit integrated solutions requiring higher system performance whose needs are not met by standard 68300 family devices. designers of high-volume applications who need to reduce cost, space, and/or power consumption. third-party technology providers who want to deliver their proprietary application-spe- cific technology to a worldwide marketplace. to develop a solution that best suits system requirements in the shortest time frame, inte- grated processor design is performed by the designer using a methodology created, tested, and documented by motorola. the resulting netlist is then laid out by motorola, verified, and fabricated in silicon. this enables flexcore integrated processors to be produced quickly and cost-effectively, with the resulting device containing all features needed for the system. to implement the application-specific logic, the designer uses motorola's standard cell library. this library offers an extensive range of design elements, memory configurations, and an expanding array of peripheral modules. each cell in the library has been designed for optimum size and performance. the added flexibility of high-speed, high-density cells allows the designer to achieve the most cost-effective solution while satisfying critical timing requirements. the standard cell library has been thoroughly characterized and maintained to ensure a smooth transition from a simulated design to working silicon. a custom part may also become a standard product if both motorola and the customer desire to do so. standard products are sold on the open market, allowing costs to be spread over additional units, resulting in lower component prices for high-volume users. third-party technology providers can use the same methodology to combine their applica- tion-specific systems expertise with a core processor. the resulting device is manufactured by motorola and can be delivered to the marketplace through either the technologist? or motorola? marketing and sales channels. figure 1-1. flexcore integrated processor typical die layout special-function block/ memory block 68000 family processor customer-designed logic special-function block/ memory block f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview 1-4 ec000 core processor user? manual motorola 1.1.1 flexcore advantages developers face tough challenges in reducing product cost. by incorporating user-designed logic and motorola-supplied functions into a single flexcore processor, a system designer can realize significant savings in cost, power consumption, board space, and pin count. the equivalent functionality can easily require 20 separate components. each component might have 16?4 pins, totaling over 350 connections. each connection is a candidate for a bad solder joint or misrouted trace. each component is another part to qualify, purchase, inven- tory, and maintain. each component requires a share of the printed circuit board. each com- ponent draws power?ften to drive large buffers and circuit board traces to get signals to another chip. each component must be individually placed and attached to a printed circuit board. the signals between the core processor unit and a peripheral might not be compat- ible nor run from the same clock, requiring time delays or other special design consider- ations. in a flexcore integrated processor, the major functions and glue logic are all properly con- nected internally, timed with the same clock, and fully tested. only essential signals are brought out to pins. the processor is assembled in a surface-mount package for the small- est possible footprint. 1.1.2 flexcore module types the three types of flexcore modules are: hard module ?ot alterable ?aid out ?as a tech file ?as a defined test scheme soft module ?etlist ?ot alterable other than by clock tree insertion ?ot laid out ?as a defined test scheme ?imulation test fixture parameterizable ?lterable via insertion of predefined parameters ?ehavioral model ?efinition of parameters defines test scheme ?ustomer selects parameter values and motorola synthesizes the design the scm68000 core processor is available as a hard module. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview motorola ec000 core processor user? manual 1-5 1.2 development cycle there are several steps that must be followed in order to create a flexcore integrated mi- croprocessor with an scm68000. figure 1-2 illustrates the standard cell design flow and the tools required to complete each step. these steps include: convert design to standard cells design?egin by implementing the required system functions with an scm68000, peripherals, memory blocks, and cells from the motorola standard cell library. capture design on workstation?se the engineering workstation to capture the logic schematic of cells and their interconnections. logic synthesis?he structural level description of the design is mapped to a more ef- ficient structural description, which is accomplished by converting the boolean equa- tions for the design to a two-level sum of products representation and minimized. generate test patterns?he stimulus and test patterns for the design are generated for the functional simulation. functional simulation?nsure that the logic of the schematic is functionally sound by using verilog, the encrypted c models and synthesis models provided by motorola. no timing information is yet associated with the simulations, and all propagation delays are preset to 1 ns. calculate node delays?motorola software (mdadecal) calculates the estimated prop- agation delays of each node in the circuit. the design software estimates delays based on the fanout, drive characteristics, and estimated interconnect capacitances of the netlist and reveals potential timing problems. path delay analysis?ith path delay information from the veritime software, the de- lays between the clocked elements of the circuit can be determined, and the critical paths that limit the clock rate can be identified. checking for setup, hold, and pulse- width violations can also be accomplished. perform real-time simulation?he real-time simulation is run to verify full functionality using the estimated propagation delays calculated by the design tools. extract test vectors?he simulator records the input/output patterns generated during the real-time simulation. the test vectors that motorola will use to test the prototypes are derived from these patterns. automatic place & route?he circuit? physical layout is created from the netlist using automatic place and route software. interconnect analysis?fter the cells are placed and routed, the interconnect capaci- tances are extracted. these capacitances replace those estimated earlier during the calculation of the node delays. re-simulate?he circuit is re-simulated with verilog to ensure no problems have aris- en due to a change in load conditions. if changes have occurred or the simulation is dif- ferent in any way, the test vectors must also be extracted again. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview 1-6 ec000 core processor user? manual motorola figure 1-2. standard cell design flow automatic place & route interconnect analysis (mdadecal) netlist comparison (lvs) pattern, mask and wafer generation assembly / test ship tested prototypes logic synthesis (synopsys) motorola customer encrypted c modules generate test patterns (stl/synopsys) calculate node delays (mdadecal) perform fault grading (verifault) perform real-time simulation (verilog) path delay analysis (veritime) extract test vectors (summit design) re-simulate (verilog) final test program convert design to standard cells capture design on workstation (composer, verilog hdl, vhdl) functional simulation (verilog) synthesis modules f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview motorola ec000 core processor user? manual 1-7 1.3 programming model the scm68000 programming model is illustrated in figure 1-3. it is separated into two modes of access: user and supervisor. the user mode provides the execution environment for the majority of application programs. the supervisor mode, which allows some additional instructions and privileges, is used by the operating system and other system software. detailed information about the programming model can be found in the m68000 family pro- grammer's reference manual (m68000pm/ad). figure 1-3. programming model 31 16 15 8 7 0 31 16 15 0 d0 d1 d2 d3 d4 d5 d6 d7 a1 a2 a3 a4 a5 a6 a0 a7 (usp) pointer pc ccr condition code register program counter user stack seven address registers eight data registers 31 70 0 (a) user programming model (b) supervisor programming model supervisor stack pointer 31 16 15 0 15 8 7 0 status register a7' (ssp) sr ccr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview 1-8 ec000 core processor user? manual motorola the user mode (see figure 1-3(a)) provides access to 16 32-bit general-purpose registers (d0?7, a0?7), a 32-bit program counter, and an 8-bit condition code register. the first eight registers (d0?7) are used as data registers for byte (8-bit), word (16-bit), and long- word (32-bit) operations. the second set of seven registers (a0?6) and the user stack pointer (a7/usp) can be used as software stack pointers and base address registers. in addition, the address registers can be used for word and long-word operations. all of the 16 registers can be used as index registers. the supervisor mode (see figure 1-3(b)) provides access to two supplementary registers, the status register (high-order byte) and the supervisor stack pointer (a7'/ssp). the status register (sr) (see figure 1-4) contains the interrupt mask (eight levels available) and the following condition codes: overflow (v), zero (z), negative (n), carry (c), and extend (x). additional status bits indicate whether the scm68000 is in the trace (t) mode and/or in the supervisor (s) state. bits 5, 6, 7, 11, 12, and 14 are undefined and reserved for future expan- sion. figure 1-4. status register t s iii xnzvc 210 15 13 10 8 4 0 trace mode supervisor state interrupt mask extend negative zero overflow carry condition codes system byte user byte f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview motorola ec000 core processor user? manual 1-9 1.4 data types and addressing modes detailed information about the data types and addressing modes can be found in the m68000 family programmer's reference manual (m68000pm/ad). the scm68000 sup- ports the five basic data types of the m68000 family: 1. bit 2. binary-coded-decimal (bcd) digit (4 bits) 3. byte (8 bits) 4. word (16 bits) 5. long word (32 bits) in addition, the instruction set supports operations on other data formats such as memory addresses, status word, data, etc. the scm68000 also supports the basic addressing modes of the m68000 family. the reg- ister indirect addressing modes support postincrementing, predecrementing, offsetting, and indexing capabilities. the program counter relative mode also supports indexing and offset- ting. table 1-1 lists a summary of the data addressing modes for the scm68000. table 1-1. data addressing modes addressing modes generation syntax register direct addressing data register direct address register direct ea = dn ea = an dn an absolute data addressing absolute short absolute long ea = (next word) ea = (next two words) (xxx).w (xxx).l program counter relative addressing relative with offset relative with index and offset ea = (pc) + d 16 ea = (pc) + d8 (d 16 ,pc) (d 8 ,pc,xn) register indirect addressing register indirect postincrement register indirect predecrement register indirect register indirect with offset indexed register indirect with offset ea = (an) ea = (an), an an + n an an n, ea = (an) ea = (an) + d 16 ea = (an) + (xn) + d8 (an) (an)+ ?an) (d 16 ,an) (d 8 ,an,xn) immediate data addressing immediate quick immediate data = next word(s) inherent data # implied addressing implied register ea = sr, usp, ssp, pc sr, usp, ssp, pc notes: ea = effective address dn = data register an = address register ( ) = contents of pc = program counter d 8 = 8-bit offset (displacement) d 16 = 16-bit offset (displacement) n = 1 for byte, 2 for word, and 4 for long word. if an is the stack pointer and the operand size is byte, n = 2 to keep the stack pointer on a word boundary. = replaces xn = address or data register used as index register sr = status register usp = user stack pointer ssp = supervisor stack pointer (xxx) = absolute address f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview 1-10 ec000 core processor user? manual motorola 1.5 data organization the eight data registers support data operands of 1, 8, 16, or 32 bits. the seven address registers and the active stack pointer support address operands of 32 bits. 1.5.1 data registers each data register is 32 bits wide. byte operands occupy the low-order 8 bits, word oper- ands, the low-order 16 bits, and long-word operands, the entire 32 bits. the least significant bit is addressed as bit zero; the most significant bit is addressed as bit 31. when a data register is used as either a source or a destination operand, only the appropri- ate low-order portion is changed; the remaining high-order portion is neither used nor changed. for example, if 8 bits are to be moved into a data register, bits 0 through 7 will be modified and bits 8 through 31 will not be changed. 1.5.2 address registers each address register (and the stack pointer) is 32 bits wide and holds a full 32-bit address. address registers do not support byte-sized operands. therefore, when an address register is used as a source operand, either the low-order word or the entire long-word operand is used, depending upon the operation size. when an address register is used as the destina- tion operand, the entire register is affected, regardless of the operation size. if the operation size is word, operands are sign-extended to 32 bits before the operation is performed. 1.5.3 data organization in memory bytes are individually addressable. as shown in figure 1-5, the high-order byte of a word has the same address as the word. the low-order byte has an odd address, one count higher. instructions and multibyte data are accessed only on word (even byte) boundaries. if a long-word operand is located at address n (n even), then the second word of that oper- and is located at address n+2. figure 1-5. word organization in memory byte 000000 byte 000001 word 0 byte 000002 byte 000003 word 1 byte fffffe byte ffffff word 7fffff 15 7 0 141312111098 654321 address $000000 $000002 $fffffe f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview motorola ec000 core processor user? manual 1-11 the data types supported by the scm68000 are bit data, integer data of 8, 16, and 32 bits, 32-bit addresses, and binary-coded-decimal data. each data type is stored in memory as shown in figure 1-6. 1.6 instruction set summary table 1-2 lists the notational conventions used throughout this manual unless otherwise specified. table 1-3 lists the scm68000 instruction set by opcode. in the syntax descrip- tions, the left operand is the source operand, and the right operand is the destination oper- and. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview 1-12 ec000 core processor user? manual motorola figure 1-6. data organization in memory msd lsd msb msb msb 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 bit data: byte 0 word 0 long word 0 long word 1 long word 2 word 1 word 2 lsb lsb lsb byte 1 byte 2 byte 3 1 byte = 8 bits 1 word = 16 bits 1 long word = 32 bits 1 address = 32 bits 2 binary coded decimal digits = 1 byte n + 1 n + 3 n n + 2 n n + 2 n + 4 n + 6 n + 8 n + 10 n n + 2 n + 4 integer data: addresses: decimal data: msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 address 0 bcd 0 bcd 1 bcd 2 bcd 3 bcd 6 bcd 7 bcd 4 bcd 5 address 1 address 2 lsb n n + 2 n + 4 n + 6 n + 8 n + 10 high order low order high order low order msd = most significant digit 1 byte = 8 bits msb = most significant bit lsb = least significant bit lsd = least significant digit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview 1-13 ec000 core processor user? manual motorola table 1-2. notational conventions single- and double-operand operations not equal. + arithmetic addition or postincrement indicator. arithmetic subtraction or predecrement indicator. arithmetic multiplication. arithmetic division or conjunction symbol. ~ invert; operand is logically complemented. l logical and v logical or logical exclusive or source operand is moved to destination operand. two operands are exchanged. < relational test; true if source operand is less than destination operand. > relational test; true if source operand is greater than destination operand. data used as an operand. tested operand is compared to zero and the condition codes are set appropriately. sign-ex- tended all bits of the upper portion are made equal to the high-order bit of the lower portion. shifted by the source operand is shifted by the number of count. rotated by the source operand is rotated by the number of count. bit number of selects a single bit of the operand. other operations trap 1 s-bit of sr; ssp ?4 ssp; pc (ssp); ssp ?2 ssp; sr (ssp); vector address pc stop enter the stopped state, waiting for interrupts. 10 the operand is bcd; operations are performed in decimal. if then else test the condition. if true, the operations after ?hen?are performed. if the condition is false and the optional ?lse?clause is present, the operations after ?lse?are performed. if the condition is false and "else" is omitted, the instruction performs no operation. refer to the bcc instruction description as an example. register specification an any address register n (example: a3 is address register 3) ax, ay source and destination address registers, respectively. dn any data register n (example: d5 is data register 5) dx, dy source and destination data registers, respectively. rn any address or data register rx, ry any source and destination registers, respectively. xn index register?n, dn, or suppressed. data format and type operand data format: byte (b), word (w), long (l) subfields and qualifiers # or # immediate data following the instruction word(s). ( ) identifies an indirect address in a register. [ ] identifies an indirect address in memory. d n displacement value, n bits wide (example: d 16 is a 16-bit displacement). register names ccr condition code register (lower byte of status register) pc program counter sr status register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview 1-14 ec000 core processor user? manual motorola register codes c carry bit in ccr cc condition codes from ccr n negative bit in ccr u undefined, reserved for motorola use v overflow bit in ccr x extend bit in ccr z zero bit in ccr stack pointers sp active stack pointer ssp supervisor (master or interrupt) stack pointer usp user stack pointer miscellaneous effective address assembly program label list of registers, for example d3?0. table 1-3. instruction set summary opcode operation syntax abcd source 10 + destination 10 + x destination abcd dy,dx abcd ?ay), ?ax) add source + destination destination add ,dn add dn, adda source + destination destination adda ,an addi immediate data + destination destination addi # , addq immediate data + destination destination addq # , addx source + destination + x destination addx dy, dx addx ?ay), ?ax) and source l destination destination and ,dn and dn, andi immediate data l destination destination andi # , andi to ccr source l ccr ccr andi # , ccr andi to sr if supervisor state then source l sr sr else trap to privilege violation trap andi # , sr asl, asr destination shifted by destination asd dx,dy asd # ,dy asd bcc if (condition true) then pc + d n pc bcc bchg ~ ( of destination) z; ~ ( of destination) of destination bchg dn, bchg # , bclr ~ ( of destination) z; 0 of destination bclr dn, bclr # , bkpt run breakpoint acknowledge cycle; trap as illegal instruction bkpt # bra pc + d n pc bra bset ~ ( of destination) z; 1 of destination bset dn, bset # , bsr sp ?4 sp; pc (sp); pc + d n pc bsr btst ~ ( of destination) z; btst dn, btst # , chk if dn < 0 or dn > source then trap to chk instruction vector chk ,dn clr 0 destination clr cmp destination ?source cc cmp ,dn table 1-2. notational conventions (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview 1-15 ec000 core processor user? manual motorola cmpa destination ?source cc cmpa ,an cmpi destination ?immediate data cc cmpi # , cmpm destination ?source cc cmpm (ay)+, (ax)+ dbcc if condition false then (dn ?1 dn; if dn ? then pc + d n pc) dbcc dn, divs destination source destination divs.w ,dn32/16 16r:16q divu destination source destination divu.w ,dn32/16 16r:16q eor source destination destination eor dn, eori immediate data destination destination eori # , eori to ccr source ccr ccr eori # ,ccr eori to sr if supervisor state then source sr sr else trap to privilege violation trap eori # ,sr exg rx ry exg dx,dy exg ax,ay exg dx,ay exg ay,dx ext destination sign-extended destination ext.w dnextend byte to word ext.l dnextend word to long word illegal ssp ?4 ssp; pc (ssp); ssp ?2 ssp; sr (ssp); illegal instruction vector address pc illegal jmp destination address pc jmp jsr sp ?4 sp; pc (sp) destination address pc jsr lea an lea ,an link sp ?4 sp; an (sp) sp an, sp + d n sp link an, # lsl,lsr destination shifted by destination lsd dx,dy lsd # ,dy lsd move source destination move , movea source destination movea ,an move to ccr source ccr move ,ccr move from sr sr destination move sr, move to sr if supervisor state then source sr else trap to privilege violation trap move ,sr move usp if supervisor state then usp an or an usp else trap to privilege violation trap move usp,an move an,usp movem registers destination; source registers movem , movem , movep source destination movep dx,(d 16 ,ay) movep (d 16 ,ay),dx moveq immediate data destination moveq # ,dn muls source destination destination muls.w ,dn16 x 16 32 mulu source destination destination mulu.w ,dn16 x 16 32 nbcd 0 ?(destination 10 ) ?x destination nbcd neg 0 ?(destination) destination neg negx 0 ?(destination) ?x destination negx nop none nop not ~destination destination not or source v destination destination or ,dn or dn, table 1-3. instruction set summary (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview 1-16 ec000 core processor user? manual motorola ori immediate data v destination destination ori # , ori to ccr source v ccr ccr ori # ,ccr ori to sr if supervisor state then source v sr sr else trap to privilege violation trap ori # ,sr pea sp ?4 sp; (sp) pea reset if supervisor state then assert resetob line else trap to privilege violation trap reset rol, ror destination rotated by destination rod dx,dy rod # ,dy rod roxl, roxr destination rotated with x by destination roxd dx,dy roxd # ,dy roxd rte if supervisor state then (sp) sr; sp + 2 sp; (sp) pc; sp + 4 sp; restore state and deallocate stack according to (sp) else trap to privilege violation trap rte rtr (sp) ccr; sp + 2 sp; (sp) pc; sp + 4 sp rtr rts (sp) pc; sp + 4 sp rts sbcd destination 10 ?source 10 ?x destination sbcd dx,dy sbcd ?ax),?ay) scc if condition true then 1s destination else 0s destination scc stop if supervisor state then immediate data sr; stop else trap to privilege violation trap stop # sub destination ?source destination sub ,dn sub dn, suba destination ?source destination suba ,an subi destination ?immediate data destination subi # , subq destination ?immediate data destination subq # , subx destination ?source ?x destination subx dx,dy subx ?ax),?ay) swap register [31:16] register [15:0] swap dn tas destination tested condition codes; 1 bit 7 of destination tas trap 1 s-bit of sr; ssp ?4 ssp; pc (ssp); ssp ?2 ssp; sr (ssp); vector address pc trap # trapv if v then trap to trapv instruciton vector trapv tst destination tested condition codes tst unlk an sp; (sp) an; sp + 4 sp unlk an note: d is direction, l or r. table 1-3. instruction set summary (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola ec000 core processor user? manual 2-1 section 2 signal description this section contains descriptions of the scm68000 (ec000 core) 1 input and output signals. the input and output signals are shown in figure 2-1. table 2-1 lists the pins, signal names, type, and whether they are three-stateable. the following paragraphs provide brief descrip- tions of the signals and references (where applicable) to other paragraphs that contain more information about the signals. note the terms assertion and negation are used extensively in this manual to avoid confusion when describing a mixture of "active- low" and "active-high" signals. the term assert or assertion is used to indicate that a signal is active or true, independently of whether that level is represented by a high or low voltage. the term negate or negation is used to indicate that a signal is inac- tive or false. 2.1 address bus (a31?0) this 32-bit, unidirectional, three-state bus is capable of addressing 4 gbytes of address space. this bus provides the address for bus operation during all cycles except interrupt acknowledge cycles. during interrupt acknowledge cycles, address lines a1, a2, and a3 provide the level number of the interrupt being acknowledged, and address lines a31?4 and a0 are driven to a logic high. 2.2 data bus (d15?0) this 16-bit, bidirectional, three-state bus is the general-purpose data-path. the data bus transfers and accepts data in either word or byte length if the scm68000 is operating in the 16-bit mode. if the scm68000 is operating in the 8-bit mode, it drives the entire bus during writes, but only the lower eight bits (d7?0) contain valid data. in the 8-bit mode, the scm68000 ignores the data on data lines d15?8 during read cycles. during an interrupt acknowledge cycle, the external device supplies the vector number on data lines d7?0. 2.3 clock (clki, clko) the clki input is internally buffered for development of the internal clocks needed by the scm68000. this clock signal is a constant-frequency square wave that requires no stretch- ing or shaping. the clock signal must conform to minimum and maximum pulse-width times 1. the scm68000 is the name of the verilog model for the ec000 core. the remainder of this section will refer to the ec000 core as only the scm68000. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
signal description 2-2 ec000 core processor user? manual motorola figure 2-1. input/output signals table 2-1. signal summary signal name mnemonic input/ output active state output circuit hi-z on haltib or stop instruction hi-z on bus relinquish or resetib address bus a31?0 output high ts no yes address output enable aoeb output low std no no address strobe asb output low ts no yes autovector avecb input low std n/a n/a bus error berrb input low std n/a n/a bus grant bgb output low std no no bus grant acknowledge bgackb input low std n/a n/a bus request brb input low std n/a n/a clock in clki input high std n/a n/a clock out clko output high std no no control output enable coeb output low std no no data bus d15?0 input/output high ts yes yes disable control disb input low std n/a n/a data output enable doeb output low std no no clki clko mode test testclk avecb berrb resetob resetib haltob haltib ipendb stop refillb statusb tscae doeb asb rwb udsb ldsb dtackb rmcb erwb dsb siz1?iz0 brb bgb bgackb a31?0 d15?0 scm68000 aoeb coeb disb fc2?c0 iplb2?plb0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
signal description motorola ec000 core processor user? manual 2-3 listed in the section 7 electrical characteristics . the clko output follows clki to provide a reference for testing. 2.4 asynchronous bus control the following signals control asynchronous data transfers: address strobe, read/write, early read/write, data strobe, upper data strobe, lower data strobe, read-modify-write, data trans- fer size, and data transfer acknowledge. these signals are described in the following para- graphs. 2.4.1 address strobe (asb) this active low, three-state signal indicates that the information on the address bus is a valid address. 2.4.2 read/write (rwb) and early read/write (erwb) the active-low, three-state rwb output signal defines the data bus transfer as a read or write cycle. the active-low, three-state erwb output signal indicates a write cycle one-half clock cycle earlier than the read/write signal. negation times are the same for both signals. these signals relate to the data strobe signals described in the following paragraphs. data strobe dsb output low ts no yes data transfer acknowledge dtackb input low std n/a n/a early read write erwb output low ts no yes function code fc2?c0 output high ts no yes halt in haltib input low std n/a n/a halt out haltob output low std no no interrupt pending ipendb output low std no no interrupt control iplb2?plb0 input low std n/a n/a lower data strobe ldsb output low ts no yes mode mode input high std n/a n/a cpu pipe refill refillb output low std no no reset in resetib input low std n/a n/a reset out resetob output low std no no read-modify-write rmcb output low ts no yes read/write rwb output low ts no yes data transfer size siz1, siz0 output high ts no yes microsequencer status indication statusb output low std no no stop stop output high std no no test test input high std n/a n/a test clock testclk output high std no no address three-state control tscae output high std no no upper data strobe udsb output low ts no yes note: ts = three-state output std = standard cmos output table 2-1. signal summary signal name mnemonic input/ output active state output circuit hi-z on haltib or stop instruction hi-z on bus relinquish or resetib f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
signal description 2-4 ec000 core processor user? manual motorola 2.4.3 upper and lower data strobes (udsb, ldsb), and data strobe (dsb) these active-low, three-state signals and rwb control the flow of data on the data bus. table 2-2 lists the combinations of these signals and the corresponding data on the bus. when the rwb line is a logic high, the scm68000 reads from the data bus. when the rwb line is a logic low, the scm68000 writes to the data bus. in the case of an 8-bit write in 16- bit mode, the same data will be on both d7?0 and d15?8. in 8-bit mode, udsb is always forced high and only the ldsb signal and rwb are used to control the flow of data on the data bus. table 2-3 lists the combinations of these signals and the corresponding data on the bus. when the rwb line is a logic high, the scm68000 reads from the data bus. when the rwb line is a logic low, the scm68000 drives the data bus. dsb is an active-low, three-state output signal that is asserted whenever ldsb or udsb is asserted. 2.4.4 data transfer acknowledge (dtackb) this active-low input indicates the completion of the data transfer. when the scm68000 rec- ognizes dtackb during a read cycle, data is latched and the bus cycle is terminated. when dtackb is recognized during a write cycle, the data bus enters a high-impedance state and the bus cycle is terminated. 2.4.5 data transfer size (siz1?iz0) these active-high, three-state output signals provide information on the size of the operand transfer. these outputs indicate the number of bytes to be transferred in the current bus cycle. table 2-4 indicates the size signal encoding. table 2-2. upper and lower data strobe control of data bus udsb ldsb rwb d15?8 d7?0 high high no valid data no valid data low low high valid data bits 15? valid data bits 7? high low high no valid data valid data bits 7? low high high valid data bits 15? no valid data low low low valid data bits 15-8 valid data bits 7? high low low valid data bits 7? valid data bits 7? low high low valid data bits 15? valid data bits 15? table 2-3. lower data strobe control of data bus ldsb rwb data bus operation high no valid data low high read cycle low low write cycle f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
signal description motorola ec000 core processor user? manual 2-5 2.4.6 read-modify-write (rmcb) this active-low, three-state output line is logic low during read-modify-write cycles and indi- cates an indivisible bus sequence. this is described in 3.1.3 read-modify-write cycle . 2.5 bus arbitration control the bus request, bus grant, and bus grant acknowledge signals form the bus arbitration con- trol signals that determine which device will be the bus master device. there are two possi- ble arbitration protocols: 2-wire and 3-wire. in the 2-wire protocol, bgackb is not used and must be negated. 2.5.1 bus request (brb) this active-low input is the combination of bus request signals from all other devices that could be bus masters. this signal indicates to the scm68000 that some other device needs to become the bus master. bus requests can be issued at any time during a cycle or between cycles. 2.5.2 bus grant (bgb) this active-low output indicates to all other potential bus master devices that the scm68000 will relinquish bus control at the end of the current bus cycle. 2.5.3 bus grant acknowledge (bgackb)?-wire protocol only this active-low input indicates that some other device has become the bus master. this sig- nal should not be asserted until the following four conditions are met: 1. a bus grant has been received. 2. address strobe is negated, which indicates that the scm68000 is not using the bus. 3. data transfer acknowledge is negated, which indicates that neither memory nor pe- ripherals are using the bus. 4. bus grant acknowledge is negated, which indicates that no other device is still claiming to be the bus master. 2.6 interrupt control (iplb2?plb0) these active-low input signals indicate the encoded priority level of the device requesting an interrupt. level 7, which cannot be masked, has the highest priority; level 0 indicates that no interrupts have been requested. iplb0 is the least significant bit of the encoded level, and iplb2 is the most significant bit. for each interrupt request, these signals must maintain the interrupt request level until the scm68000 acknowledges the interrupt to guarantee that table 2-4. data transfer size size code output siz1 siz0 size 1 0 byte 0 1 word f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
signal description 2-6 ec000 core processor user? manual motorola the interrupt is recognized. table 2-5 lists the interrupt levels, the states of iplb2?plb0 that define each level, and the mask value that allows an interrupt at each level. 2.7 system control the system control inputs are used to reset, halt, disable, and test the scm68000 as well as signal a bus error to the scm68000 and choose either the 8-bit or 16-bit mode. the two outputs reset the external devices in the system and signal to those devices when the scm68000 has stopped executing instructions because of an error. the system control sig- nals are described in the following paragraphs. 2.7.1 bus error (berrb) this input signal indicates a problem in the current bus cycle. the problem may be the fol- lowing: 1. no response from a device. 2. no interrupt vector number returned. 3. an illegal access request rejected by a memory management unit. 4. some other application-dependent error. the scm68000 either retries the bus cycle or performs exception processing, as deter- mined by interaction between the bus error signal and the halt signal. 2.7.2 reset external/internal (resetib, resetob) the assertion of the active-low input, resetib can start a system initialization sequence by resetting the scm68000. the scm68000 assertion of resetob (from executing a reset instruction) resets all external devices of a system without affecting the internal state of the scm68000. the interaction of resetib, resetob, and haltib is described in 4.3.1 reset . 2.7.3 halt external/internal (haltib, haltob) asserting the active-low input, haltib causes the scm68000 to stop bus activity at the completion of the current bus cycle. this operation places all control signals in the inactive state and places the data bus in a high-impedance state (see table 2-1). table 2-5. interrupt levels and mask values requested interrupt level control line status interrupt mask level required for recognition iplb2 iplb1 iplb0 0 high high high no interrupt is requested 1 high high low 0 2 high low high 1? 3 high low low 2? 4 low high high 3? 5 low high low 4? 6 low low high 5? 7 low low low 7? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
signal description motorola ec000 core processor user? manual 2-7 when the scm68000 has stopped executing instructions (in the case of a double bus fault condition, for example), the active-low output, haltob, is asserted by the scm68000 to indicate the condition to external devices. 2.7.4 mode (mode) this input selects between the 8-bit and 16-bit operating modes. if this input is grounded during reset, the scm68000 comes out of reset in the 8-bit mode. if this input is tied to a logic high during reset, the scm68000 comes out of reset in the 16-bit mode. changing this input during normal operation may produce unpredictable results. 2.7.5 disable control (disb) this active-low signal is designed to place the scm68000 into a quiescent state allowing other sections of the circuit to be tested without interference from the scm68000. when this signal is asserted, the scm68000 responds with the following with minimum gate delay if the clock is stopped: all three-state outputs will be placed into a high-impedance state. the bus grant (bgb), clock output (clko), halt output (haltob), reset output (rese- tob), microsequencer status (statusb), stop instruction indicator (stop), and test clock (testclk) signals remain at the state they were in when the clock was stopped. the remaining outputs are disabled, forcing them into an inactive state. if the clock is running, the scm68000 responds with the following with minimum gate delay: all three-state outputs will be placed into a high-impedance state. the clock output (clko) continues to follow the clock input (clki). the microsequencer status (statusb) signal is forced to a logic low. the test clock (testclk) signal is forced to a logic low. the remaining outputs are disabled, forcing them into their inactive states. when disb is asserted, it is internally gated with the internal scm68000 reset and halt signals after the input synchronizer. the user must ensure that the system is reset as dis- cussed in 4.3.1 reset . 2.7.6 test mode (test) this active-high input signal allows the scm68000 to enter the test mode. this permits application of standard m68000 family test mode patterns to the scm68000. 2.7.7 test clock (testclk) if the scm680000 is properly reset during simulation, the testclk signal will begin to pulse. a single period of the test clock consists of ten scm68000 clock periods (six clocks low, four clocks high). this signal is generated by an internal ring counter that may come up in any state. (at power-on, it is impossible to guarantee phase relationship of testclk to clki.) the testclk signal is a free-running clock that runs regardless of the state of the mpu bus. for more information on resetting the scm68000 for simulation, see 4.3.1.2 ini- tializing the scm68000 for simulation . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
signal description 2-8 ec000 core processor user? manual motorola 2.7.8 autovector (avecb) this active-low input signal indicates that the scm68000 should use automatic vectoring for an interrupt during an interrupt acknowledge cycle. avecb should be asserted only during an interrupt acknowledge cycle or erratic controller operation may occur. 2.8 three-state control the following signals are the enable signals to put scm68000 signals into a high-impedence state. 2.8.1 address output enable (aoeb) this active-low output signal is negated to put the address lines (a31?0), function codes (fc2?c0), size codes (siz1?iz0), early read/write (erwb), and read/write (rwb) into a high-impedance state. 2.8.2 control output enable (coeb) this active-low output signal is negated to put the address strobe (asb), data strobe (dsb), lower data strobe (ldsb), read-modify-write (rmcb), and upper data strobe (udsb) into a high-impedance state. 2.8.3 data output enable (doeb) this active-low output signal is negated to put the data lines of the scm68000 into a high- impedance state. 2.9 processor status these signals are used to indicate pending interrupts and when the scm68000 is between bus cycles or at instruction boundaries. they also show when the instruction pipe is refilling and when the processor has been stopped. the signals are described in the following para- graphs. 2.9.1 function codes (fc2?c0) these active-high, three-state function code outputs indicate the mode (user or supervisor) and the address space currently being accessed as listed in table 2-6. the function code outputs are valid whenever asb is active. table 2-6. function code outputs function code output cycle time fc2 fc1 fc0 low low low (undefined, reserved) low low high user data low high low user program low high high (undefined, reserved) high low low (undefined, reserved) high low high supervisor data high high low supervisor program high high high interrupt acknowledge f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
signal description motorola ec000 core processor user? manual 2-9 2.9.2 address three-state control (tscae) this active-high output signal is asserted between bus cycle accesses of the scm68000. 2.9.3 stop instruction indicator (stop) this output line pulses at one fourth the rate of the clki signal with an active time of one clock period when the stop instruction is executed. 2.9.4 interrupt pending (ipendb) this active-low output signal indicates a valid interrupt has been recognized. 2.9.5 cpu pipe refill (refillb) this active-low output signal is asserted for one clock period to indicate that a refill of the cpu pipe is occurring due to a change in program flow. this is used for emulator support. 2.9.6 microsequencer status indication (statusb) this active-low output signal indicates microsequencer status and is used for emulator sup- port. the number of clock cycles for which this signal is asserted indicates the status of the scm68000. when the scm68000 approaches an instruction boundary, this signal is nor- mally asserted for one clock cycle. table 2-7 indicates exceptions that are indicated by the assertion of this signal for more than one cycle. 2.10 multiplexing pins when a design is implemented, certain pins need to be multiplexed to the pads for testing purposes. motorola recommends that all the pins on the scm68000 be multiplexed to offer a means for testing the processor with test vectors provided by motorola. this will provide maximum fault coverage. varying degrees of fault coverage can be obtained depending on which pins the user does or does not multiplex. table 2-7. status indication exceptions asserted for indicates one clock sequencer at instruction boundary - will begin execution of next instruction two clocks sequencer at instruction boundary - will not begin the next instruction immediately due to: ?pending interrupt exception or ?pending trace exception or ?illegal instruction exception or ?pending breakpoint instruction exception or ?privileged instruction exception three clocks exception processing to begin for: ?bus error or ?address error or ?a-line instruction or ?spurious interrupt or ?illegal instruction or ?privileged instruction or ?auto vectored interrupt or ?f-line instruction continuously core is: ?halted ?reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
signal description 2-10 ec000 core processor user? manual motorola all pins must be multiplexed according to the requirements in table 2-8. however, it is nec- essary that the proper three-state control signal be used to control the three-state drivers as stated in 2.8 three-state control . table 2-8 shows a list of pins and the priority with which they need to be multiplexed. the priority column has three possible responses: required, required if used, not required, and internal. the ?equired if used?response means that the pin must be muxed out if the pin is used in the current design. the "internal" response means that the signal may be used internally and must not be muxed out. table 2-8. pin multiplexing priority signal name pin name input/output priority address bus a31?24 output required if used address bus a23?0 output required address output enable aoeb output internal address strobe asb output required bus error berrb input required bus grant bgb output required bus grant acknowledge bgackb input required bus request brb input required clock in clki input required clock out clko output required if used control output enable coeb output internal data bus d15?0 input/output required disable control disb input internal data output enable doeb output internal data strobe dsb output required if used data transfer acknowledge dtackb input required test clock testclk output not required early read write erwb output required if used function code fc2?c0 output required halt in* haltib input required halt out* haltob output required interrupt pending ipendb output required if used interrupt control iplb2?plb0 input required lower data strobe ldsb output required mode mode input required cpu pipe refill refillb output required if used reset in* resetib input required reset out* resetob output required read-modify-write rmcb output required if used read/write rwb output required data transfer size siz1, siz0 output required if used microsequencer status indication statusb output required if used stop stop output required if used test test input required address three-state control tscae output required if used upper data strobe udsb output required autovector avecb input required * haltib and haltob may share a single pin, haltb, that is functionally equivalent to the circuit in figure 4-10. resetib and resetob may share a single pin, resetb, that is functionally equivalent to the circuit in figure 4-10. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
signal description 2-11 ec000 core processor user? manual motorola disb must be negated by the pin multiplexing circuitry. if haltob and/or resetob are multiplexed to a three-state output, the internal pin multiplexing circuitry must assert the appropriate output enable. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
signal description 2-12 ec000 core processor user? manual motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola ec000 core processor user? manual 3-1 section 3 bus operation this section describes control signals and bus operation during data transfer operations, bus arbitration, and bus error and halt conditions. note the terms assertion and negation are used extensively in this manual to avoid confusion when describing a mixture of ?ctive- low?and ?ctive-high?signals. the term assert or assertion is used to indicate that a signal is active or true, independently of whether that level is represented by a high or low voltage. the term negate or negation is used to indicate that a signal is inac- tive or false. 3.1 data transfer operations transfer of data between devices involves the following signals: 1. address bus (a31?0) 2. data bus (d7?0 and/or d15?8) 3. control signals the address and data buses are separate parallel buses used to transfer data using an asynchronous bus protocol. control signals indicate the beginning and type of a bus cycle as well as the address space and size of the transfer. the selected device then controls the length of the cycle by terminating it using the control signals. in all bus cycles, the bus master assumes responsibility for de-skewing the acknowledge and data signals from the slave device. the scm68000 (ec000 core) 1 operates in either of two modes: 8-bit or 16-bit mode. the 8- bit mode is selected by grounding the mode pin while the 16-bit mode is selected by pulling the mode pin to a logic high (see 2.7.4 mode (mode) for more information on the mode signal). during operation in the 8-bit mode, all bus cycles use ldsb, and one byte of data is trans- ferred on data bus bits d7 through d0. udsb is never asserted, and data bus bits d15 through d8 are undefined. for word or long-word operations, data is transferred in two and four bus cycles, respectively. 1. the scm68000 is the name of the verilog model for the ec000 core. the remainder of this section will refer to the ec000 core as only the scm68000. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation 3-2 ec000 core processor user? manual motorola during operation in the 16-bit mode, byte operations can occur on either d15?8 or d7?0, depending on a0. if a0 is zero, the upper byte is used and udsb is asserted. if a0 is one, the lower byte is used and ldsb is asserted. for word and long-word operations, a0 is always zero, data bits d15 through d0 are used, and both ldsb and udsb are asserted. for long-word operations, data is transferred in two bus cycles with a1 indicating which half of the long word is being transferred. the actual order of the long-word halves is instruction and address-mode dependent. the following paragraphs describe the read cycle, write cycle, read-modify-write cycle, and cpu space cycle. the indivisible read-modify-write cycle allows interlocked multiprocessor communications. a cpu space cycle is a special cycle used for interrupt acknowledge cycles. 3.1.1 read cycle during a read cycle, the scm68000 receives data from memory or from a peripheral device. when data is received, the scm68000 correctly positions the byte internally. the word read cycle flowchart is shown in figure 3-1. the byte read cycle flowcharts for the 8-bit and 16-bit modes are shown in figure 3-2 and figure 3-3, respectively. the read cycle and write cycle timing diagrams are shown in figure 3-4 and figure 3-5. the word and byte read cycle timing diagram for operation in the 16-bit mode is shown in figure 3-6. figure 3-1. word read cycle flowchart for 16-bit mode bus master address the device 1) set rwb and erwb to read 2) place function code on fc2?c0 3) place address on a31?0 4) assert address strobe (asb) 5) assert upper data strobe (udsb), lower data strobe (ldsb), and data strobe (dsb) acquire the data 1) latch data 2) negate udsb, ldsb, and dsb 3) negate asb terminate the cycle output the data 1) decode address 2) place data on d15?0 3) assert data transfer acknowledge (dtackb) 1) remove data from d15?0 2) negate dtackb slave start next cycle f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation motorola ec000 core processor user? manual 3-3 figure 3-2. byte read cycle flowchart for 8-bit mode figure 3-3. byte read cycle flowchart for 16-bit mode bus master address the device 1) set rwb and erwb to read 2) place function code on fc2?c0 3) place address on a31?0 4) assert address strobe (asb) 5) assert lower data strobe (ldsb) acquire the data 1) latch data 2) negate ldsb and dsb 3) negate asb terminate the cycle output the data 1) decode address 2) place data on d7?0 3) assert data transfer acknowledge (dtackb) 1) remove data from d7?0 2) negate dtackb slave start next cycle and data strobe (dsb) bus master address the device 1) set rwb and erwb to read 2) place function code on fc2?c0 3) place address on a31-a0 4) assert address strobe (asb) 5) assert upper data strobe (udsb) or lower data strobe (ldsb) (based on a0), and data strobe (dsb) acquire the data 1) latch data 2) negate udsb, ldsb, and dsb 3) negate asb terminate the cycle output the data 1) decode address 2) place data on d7?0 or d15?8 (based on udsb or ldsb) 3) assert data transfer acknowledge (dtackb) 1) remove data from d7?0 or d15?8 2) negate dtackb slave start next cycle f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation 3-4 ec000 core processor user? manual motorola figure 3-4. read and write cycle timing diagram for 8-bit mode s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 w w w w s5 s6 s7 clki fc2?c0 a31?0 asb dsb ldsb rwb dtackb d7?0 read write 2 wait state read erwb tscae doeb aoeb coeb rmcb siz1?iz0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation motorola ec000 core processor user? manual 3-5 figure 3-5. read and write cycle timing diagram for 16-bit mode s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 w w w w s5 s6 s7 clki fc2?c0 a31?0 asb udsb ldsb rwb dtackb d15?8 d7?0 read write 2 wait state read dsb erwb doeb siz1?iz0 tscae aoeb coeb rmcb a0=0 a0=0 a0=0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation 3-6 ec000 core processor user? manual motorola a bus cycle has a minimum of eight states. the various signals are asserted during specific states of a read cycle, as follows: state 0 the read cycle starts in state 0 (s0). the scm68000 places valid function codes on fc2 fc0, and a valid address on the address bus. rwb and erwb are driven to logic highs to identify a read cycle, and tscae is driven to a logic high to indicate that the scm68000 is between bus cycles. figure 3-6. word and byte read cycle timing diagram for 16-bit mode s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 s5 s6 s7 clki fc2?c0 a31?0 asb udsb ldsb rwb dtackb d15?8 d7?0 word read odd byte read even byte read dsb erwb aoeb coeb doeb rmcb siz1?iz0 tscae a0=0 a0=1 a0=0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation motorola ec000 core processor user? manual 3-7 state 1 entering state 1 (s1), tscae is driven low to indicate the beginning of the bus cycle. state 2 on the rising edge of state 2 (s2), the scm68000 asserts asb, udsb, ldsb, and dsb. state 3 during state 3 (s3), no bus signals are altered. state 4 during state 4 (s4), the scm68000 waits for a cycle termination signal (dtackb or berrb) if neither termination signal is asserted before the falling edge at the end of s4, the scm68000 inserts wait states (full clock cycles) until either dtackb or berrb is as- serted. see 3.7 the relationship of dtackb, berrb, and haltib for a description of how dtackb and berrb interact. case 1: dtackb is received alone or with berrb (see 3.4 bus error and halt opera- tion ). state 5 during state 5 (s5), no bus signals are altered. state 6 sometime between state 2 (s2) and state 6 (s6), data from the device is driven onto the data bus. state 7 on the falling edge of the clock entering state 7 (s7), the scm68000 latches data from the addressed device and negates asb, udsb, ldsb, and dsb. the device negates dtackb or berrb at this time. case 2: berrb is received without dtackb (see 3.4 bus error and halt operation ). state 5 during state 5 (s5), no bus signals are altered. state 6 during state 6 (s6), no bus signals are altered. state 7 during state 7 (s7), no bus signals are altered. state 8 during state 8 (s8), no bus signals are altered. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation 3-8 ec000 core processor user? manual motorola state 9 during state 9 (s9), asb, udsb, ldsb, and dsb are negated. the device negates berrb at this time. 3.1.2 write cycle during a write cycle, the scm68000 sends data to the memory or to a peripheral device. the word write cycle flowchart is shown in figure 3-7. the byte write cycle flowcharts for the 8-bit and 16-bit modes are shown in figure 3-8 and figure 3-9, respectively. the byte write cycle timing diagram for the 8-bit mode of operation is shown in figure 3-10. the word and byte write cycle for the 16-bit mode of operation is shown in figure 3-11. figure 3-7. word write cycle flowchart for 16-bit mode bus master address the device 1) place function code on fc2?c0 2) place address on a31?0 3) assert address strobe (asb) 4) set rwb and erwb to write 5) place data on d15?0 6) assert upper data strobe (udsb), lower data strobe (ldsb), and data strobe (dsb) 1) negate udsb, ldsb, and dsb 2) negate asb 3) remove data from d15?0 4) set rwb and erwb to read terminate the cycle input the data 1) decode address 2) store data on d15?0 3) assert data transfer acknowledge (dtackb) slave start next cycle terminate output transfer 1) negate dtackb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation motorola ec000 core processor user? manual 3-9 figure 3-8. byte write cycle flowchart for 8-bit mode figure 3-9. byte write cycle flowchart for 16-bit mode bus master address the device 1) place function code on fc2?c0 2) place address on a31?0 3) assert address strobe (asb) 4) set rwb and erwb to write 5) place data on d7?0 6) assert lower data strobe (ldsb) and data strobe (dsb) 1) negate ldsb and dsb 2) negate asb 3) remove data from d7?0 4) set rwb and erwb to read terminate the cycle input the data 1) decode address 2) store data on d7?0 3) assert data transfer acknowledge (dtackb) slave start next cycle terminate output transfer 1) negate dtackb bus master address the device 1) place function code on fc2?c0 2) place address on a31?0 3) assert address strobe (asb) 4) set rwb and erwb to write 5) place data on d7?0 or d15?8 (according to a0) 6) assert upper data strobe (udsb) or lower data strobe (ldsb) and data strobe (dsb) (based on a0) 1) negate udsb, ldsb, and dsb 2) negate asb 3) remove data from d7?0 or d15?8 4) set rwb and erwb to read terminate the cycle input the data 1) decode address 2) store data on d7?0 if ldsb is asserted. store data on d15?8 if udsb is asserted 3) assert data transfer acknowledge (dtackb) slave start next cycle terminate output transfer 1) negate dtackb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation 3-10 ec000 core processor user? manual motorola figure 3-10. write cycle timing diagram for 8-bit mode s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 s5 s6 s7 clki asb even byte write odd byte write even byte write aoeb coeb tscae rmcb rwb dtackb fc2?c0 a31?0 siz1?iz0 erwb ldsb dsb d7?0 doeb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation motorola ec000 core processor user? manual 3-11 the descriptions of the eight states of a write cycle are as follows: state 0 the write cycle starts in state 0 (s0). the scm68000 places valid function codes on fc2 fc0 and a valid address on the address bus. rwb and erwb are driven to a logic high. tscae is driven to a logic high to indicate that the scm68000 is between bus cycles. state 1 entering state 1 (s1), the scm68000 drives tscae and erwb to logic lows. figure 3-11. word and byte write cycle timing diagram for 16-bit mode s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 s5 s6 s7 clki fc2?c0 asb udsb ldsb dtackb d15?8 rwb erwb aoeb coeb tscae word write odd byte write even byte write doeb rmcb dsb a31?0 a0=0 a0=0 a0=1 d7?0 siz1?iz0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation 3-12 ec000 core processor user? manual motorola state 2 on the rising edge of state 2 (s2), the scm68000 asserts asb and drives rwb to a logic low. state 3 during state 3 (s3), the data bus is driven out of the high-impedance state as data is placed on the bus. state 4 at the rising edge of state 4 (s4), the scm68000 asserts dsb, and udsb and/or ldsb. the scm68000 waits for a cycle termination signal (dtackb or berrb). if neither ter- mination signal is asserted before the falling edge at the end of s4, the scm68000 inserts wait states (full clock cycles) until either dtackb or berrb is asserted. see 3.7 the re- lationship of dtackb, berrb, and haltib for a description of how dtackb and berrb interact. case 1: dtackb is received alone or with berrb (see 3.4 bus error and halt opera- tion ). state 5 during state 5 (s5), no bus signals are altered. state 6 during state 6 (s6), no bus signals are altered. state 7 on the falling edge of the clock entering state 7 (s7), the scm68000 negates asb, udsb, ldsb, and dsb. as the clock rises at the end of s7, the scm68000 places the data bus in the high-impedance state and drives rwb and erwb to a logic high. the device ne- gates dtackb or berrb at this time. case 2: berrb is received without dtackb (see 3.4 bus error and halt operation ). state 5 during state 5 (s5), no bus signals are altered. state 6 during state 6 (s6), no bus signals are altered. state 7 during state 7 (s7), no bus signals are altered. state 8 during state 8 (s8), no bus signals are altered. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation motorola ec000 core processor user? manual 3-13 state 9 during state 9 (s9), asb, udsb, ldsb, and dsb are negated. the device negates berrb at this time. at the end of s9, the data bus is placed in the high-impedance state, and rwb and erwb are driven to a logic high. 3.1.3 read-modify-write cycle the read-modify-write cycle performs a read operation, modifies the data in the arithmetic logic unit, and writes the data back to the same address. the address strobe (asb) remains asserted throughout the entire cycle, making the cycle indivisible. the test and set (tas) instruction uses this cycle to provide a signaling capability without deadlock between pro- cessors in a multiprocessing environment. the tas instruction (the only instruction that uses the read-modify-write cycle) only operates on bytes. thus, all read-modify-write cycles are byte operations. the read-modify-write flowchart is shown in figure 3-12 and the timing diagram is shown in figure 3-13. figure 3-12. read-modify-write cycle flowchart bus master address the device 1) set rwb and erwb to read 2) place function code on fc2?c0 3) place address on a31?0 4) assert address strobe (asb) 5) assert upper data strobe (udsb) or lower data strobe (ldsb) and data strobe (dsb) 6) assert rmcb terminate the cycle output the data 1) decode address 2) place data on d7?0 or d15?8 3) assert data transfer acknowledge (dtackb) slave start next cycle 1) remove data from d7?0 or d15?8 2) negate dtackb 1) latch data 1) negate udsb and ldsb 2) start data modification acquire the data start output transfer 1) set rwb and erwb to write 2) place data on d7?0 or d15?8 3) assert upper data strobe (udsb) or lower data strobe (ldsb) and data strobe (dsb) terminate output transfer 1) negate udsb and ldsb 2) negate asb 3) remove data from d7?0 or d15?8 4) set rwb and erwb to read input the data 1) store data on d7?0 or d15?8 2) assert data transfer acknowledge (dtackb) terminate the cycle 1) negate dtackb 5) negate rmcb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation 3-14 ec000 core processor user? manual motorola the descriptions of the read-modify-write cycle states are as follows: state 0 the read cycle starts in state 0 (s0). the scm68000 places valid function codes on fc2 fc0 and a valid address on the address bus. rwb and erwb are driven to a logic high to identify a read cycle, and tscae is driven to a logic high to indicate that the scm68000 is between bus cycles. state 1 entering state 1 (s1), tscae is driven low to indicate the beginning of the bus cycle, and rmcb is driven low to indicate a read-modify-write cycle. figure 3-13. read-modify-write cycle timing diagram clki a31?0 asb s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 s18 s19 udsb or ldsb rwb dtackb d7?0 fc2?c0 dsb erwb d15?8 aoeb coeb doeb rmcb siz1?iz0 tscae indivisible cycle f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation motorola ec000 core processor user? manual 3-15 state 2 on the rising edge of state 2 (s2), the scm68000 asserts asb, udsb or ldsb, and dsb. state 3 during state 3 (s3), no bus signals are altered. state 4 during state 4 (s4), the scm68000 waits for a cycle termination signal (dtackb or berrb). if neither termination signal is asserted before the falling edge at the end of s4, the scm68000 inserts wait states (full clock cycles) until either dtackb or berrb is as- serted. see 3.7 the relationship of dtackb, berrb, and haltib for a description of how dtackb and berrb interact. case read 1: only dtack is received. state 5 during state 5 (s5), no bus signals are altered. state 6 during state 6 (s6), data from the device is driven onto the data bus. state 7 on the falling edge of the clock entering state 7 (s7), the scm68000 accepts data from the device and negates udsb or ldsb, and dsb. the device negates dtackb at this time. states 8?1 the bus signals are unaltered during state 8 (s8)through state 11 (s11), during which the arithmetic logic unit makes appropriate modifications to the data. state 12 the write portion of the cycle starts in state 12 (s12). the valid function codes on fc2 fc0, the address bus lines, asb, rwb, and erwb remain unaltered. state 13 during state 13 (s13), erwb is driven to a logic low. state 14 on the rising edge of state 14 (s14), the scm68000 drives rwb to a logic low. state 15 during state 15 (s15), the data bus is driven out of the high-impedance state as data is placed on the bus. state 16 during state 16 (s16), the scm68000 waits for a cycle termination signal (dtackb or berrb). if neither termination signal is asserted before the falling edge at the end of s16, f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation 3-16 ec000 core processor user? manual motorola the scm68000 inserts wait states (full clock cycles) until either dtackb or berrb is as- serted. also, on the rising edge of s16, the scm68000 asserts udsb or ldsb, and dsb. case write 1: dtackb is received alone or with berrb (see 3.4 bus error and halt operation ). state 17 during state 17 (s17), no bus signals are altered. state 18 during state 18 (s18), no bus signals are altered. state 19 on the falling edge of the clock entering state 19 (s19), the scm68000 negates asb, udsb or ldsb, and dsb. as the clock rises at the end of s19, the scm68000 places the data bus in the high-impedance state and drives rwb and erwb to a logic high. the de- vice negates dtackb or berrb at this time. case read 2: dtackb and berrb are received (see 3.4 bus error and halt opera- tion ). state 5 during state 5 (s5), no bus signals are altered. state 6 during state 6 (s6), no bus signals are altered and data from the device is ignored. state 7 during state 7 (s7), udsb or ldsb, and dsb are negated. states 8?0 the bus signals are unaltered during state 8 (s8) through state 10 (s10). state 11 during state 11 (s11), asb, is negated. the cycle terminates without the write portion of the cycle. case read 3: only berrb is received (see 3.4 bus error and halt operation ). states 5? the bus signals are unaltered during state 5 (s5) through state 8 (s8). state 9 during state 9 (s9), udsb or ldsb, and dsb are negated. state 10 during state 10 (s10), no bus signals are altered. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation motorola ec000 core processor user? manual 3-17 state 11 during state 11 (s11), asb, is negated. the cycle terminates without the write portion of the cycle. case write 2: only berrb is received (see 3.4 bus error and halt operation ). states 17?0 the bus signals are unaltered during state 17 (s17) through state 20 (s20). state 21 during state 21 (s21), the scm68000 negates asb, udsb or ldsb, and dsb. rmcb is driven to a logic high after asb is negated and before the falling edge of s1 of the next bus cycle. however, the value of rmcb is not guaranteed between bus cycles after asb is negated for the cases described in this section. 3.2 bus arbitration bus arbitration is a technique used by bus master devices to request, to be granted, and to acknowledge bus mastership. bus arbitration consists of the following: 1. asserting a bus mastership request 2. receiving a grant indicating that the bus is available at the end of the current bus cycle 3. acknowledging that mastership has been assumed (3-wire bus arbitration only) there are two ways to arbitrate the scm68000 bus, 3-wire and 2-wire bus arbitration. figure 3-14 and figure 3-16 show 3-wire bus arbitration and figure 3-15 and figure 3-17 show 2- wire bus arbitration. bgackb must be negated for 2-wire bus arbitration. the timing diagram in figure 3-16 shows that the bus request is negated within 1.5 clocks of the time that an acknowledge is asserted. this situation occurs when just one external device is requesting the bus. in systems having several devices that can be bus masters, bus request lines from these devices can be ored at the scm68000, and more than one bus request signal could occur. the bus grant signal is negated 1.5 to 3.5 clock cycles after the assertion of the bus grant acknowledge signal. however, if bus request remains asserted (more than one device is requesting the bus), the scm68000 reasserts bus grant for another request a few clock cycles after bus grant (for the previous request) is negated. in response to this additional assertion of bus grant, external arbitration circuitry selects the next bus master before the current bus master has completed the bus activity. the timing diagram in figure 3-17 shows just one external device requesting the bus. the 2-wire bus arbitration is best suited to systems with just one device, besides the cpu, capa- ble of being bus master. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation 3-18 ec000 core processor user? manual motorola 3.2.1 requesting the bus external devices capable of becoming bus masters assert brb to request the bus. this sig- nal can be ored (not necessarily constructed from open-collector devices) from any of the devices in the system that can become bus master. the scm68000, which is at a lower bus priority level than the external devices, relinquishes the bus after it completes the current bus cycle. when no acknowledge is received before the bus request signal is negated, the scm68000 continues to use the bus. also, bgackb allows arbitration time for another bus master to be overlapped with bus cycles to lessen bus idle time. 3.2.2 receiving the bus grant after brb is asserted, the scm68000 asserts bgb immediately following internal synchro- nization. the exception to this is when the scm68000 has made an internal decision to exe- cute the next bus cycle but has not yet asserted asb for that cycle. in this case, bgb is delayed until asb is asserted to indicate to external devices that a bus cycle is in progress. figure 3-14. 3-wire bus arbitration cycle flowchart grant bus arbitration request the bus 1) assert bus request (brb) requesting device 1) external arbitration deter- mines next bus master 2) next bus master waits for current cycle to complete 3) next bus master asserts bus grant acknowledge (bgackb) to become new master 4) bus master negates brb terminate arbitration 1) negate bgackb processor 1) assert bus grant (bgb) acknowledge bus mastership operate as bus master 1) perform data transfers (read and write cycles) according to the same rules the pro- cessor uses rearbitrate or resume processor operation release bus mastership 1) negate bgb (and wait for bgackb to be negated) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation motorola ec000 core processor user? manual 3-19 bgb can be routed through a daisy-chained network or through a specific priority-encoded network. any method of external arbitration that observes the protocol can be used. 3.2.3 acknowledgment of mastership (3-wire bus arbitration only) upon receiving bgb, the requesting device waits until asb, dtackb, and bgackb are negated before asserting bgackb. the negation of asb indicates that the previous bus master has completed its cycle. (no device is allowed to assume bus mastership while asb is asserted.) the negation of bgackb indicates that the previous master has released the bus. the negation of dtackb indicates that the previous slave has terminated the connec- tion to the previous master. (in some applications, dtackb might not be included in this function; general-purpose devices would be connected using asb only.) when bgackb is asserted, the asserting device is bus master until it negates bgackb. bgackb should not be negated until after the bus cycle(s) is complete. a device relinquishes control of the bus by negating bgackb. the bus request from the granted device should be negated after bgackb is asserted. if another bus request is pending, bgb is reasserted within a few clocks, as described in 3.3 bus arbitration control . the scm68000 does not perform any external bus cycles before reasserting bgb. figure 3-15. 2-wire bus arbitration cycle flowchart grant bus arbitration request the bus 1) assert bus request (brb) requesting device 1) negate bus request (brb) processor 1) assert bus grant (bgb) operate as bus master rearbitrate or resume processor operation release bus mastership acknowledge release of bus mastership 1) negate bus grant (bgb) 1) external arbitration deter- mines next bus master 2) next bus master waits for current cycle to complete 3) perform data transfers (read and write cycles) according to the same rules the pro- cessor uses f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation 3-20 ec000 core processor user? manual motorola figure 3-16. 3-wire bus arbitration timing diagram clki fc2?c0 a31?0 asb dsb rwb dtackb d15?8 brb bgb s0 s6 s2 s4 s0 s2 s4 s6 s0 s2 s4 s6 s0 s2 s4 s6 processor dma device processor dma device s0 s2 s4 s6 s0 s2 s4 udsb and/or ldsb erwb d7?0 aoeb coeb doeb rmcb siz1?iz0 tscae bgackb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation motorola ec000 core processor user? manual 3-21 figure 3-17. 2-wire bus arbitration timing diagram clki fc2?c0 a31?0 asb dsb rwb dtackb d15?8 brb bgb s0 s6 s2 s4 s0 s2 s4 s6 s0 s2 s4 s6 s0 s2 s4 s6 processor dma device processor dma device s0 s2 s4 s6 s0 s2 s4 udsb and/or ldsb erwb d7?0 aoeb coeb doeb rmcb siz1?siz0 tscae f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation 3-22 ec000 core processor user? manual motorola 3.3 bus arbitration control the asynchronous bus arbitration signals are synchronized before being used internally. see 3.5 asynchronous operation for more information on the synchronization of these signals. bus arbitration control is implemented with a finite state machine. state diagram (a) in figure 3-18 applies for 3-wire bus arbitration and state diagram (b) applies for 2-wire bus arbitra- tion, in which bgackb is permanently negated internally or externally. the same finite state machine is used, but it is effectively a three-state machine because bgackb is always negated. in figure 3-18, input signals r (bus request internal) and a (bus grant acknowledge internal) are the internally synchronized versions of brb and bgackb. the bgb output is shown as g (bus grant), and the internal three-state control signal is shown as t (three-state control to bus control logic). if t is true, the address, data, and control buses are placed in the high- impedance state when asb is negated. all signals are shown in positive logic (active high), regardless of their true active voltage level. state changes (valid outputs) occur on the next rising edge of the clock after the internal signal is valid. a timing diagram of the bus arbitration sequence during an scm68000 bus cycle is shown in figure 3-19 and figure 3-22. the bus arbitration timing while the bus is inactive (e.g., the scm68000 is performing internal operations for a multiply instruction) is shown in figure 3- 20 and figure 3-23. when a bus request is made after the scm68000 has begun a bus cycle and before asb has been asserted (s0), the special sequence shown in figure 3-21 and figure 3-24 applies. instead of being asserted on the next rising edge of clock, bgb is delayed until the second rising edge following its internal assertion. figure 3-19, figure 3-20, and figure 3-21 apply for 3-wire bus arbitration. figure 3-22, fig- ure 3-23, and figure 3-24 apply for 2-wire bus arbitration. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation motorola ec000 core processor user? manual 3-23 figure 3-18. bus arbitration unit state diagrams ra xx ra ra ra xx xa ra rx 1 1 r = bus request internal a = bus grant acknowledge internal g = bus grant t = three-state control to bus control logic x = don't care notes: 1. state machine will not change if the bus is s0 or s1. refer to 3.3 bus arbitration control 2. the address bus will be placed in the high-impedance state if t is asserted and asb is negated. r r x r r (a) 3-wire bus arbitration (b) 2-wire bus arbitration gt gt gt gt ra ra ra ra xa ra gt ra gt gt gt gt gt r+a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation 3-24 ec000 core processor user? manual motorola figure 3-19. 3-wire bus arbitration timing diagram?cm68000 active s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 s5 s6 s7 s0 s 1 clki bus three-stated bgb asserted brb valid internal brb sampled brb asserted bus released from three state and processor starts next bus cycle bgackb negated internal bgackb sampled bgackb negated brb bgb bgackb fc2?c0 a31?0 asb udsb and/or lsdb dsb rwb dtackb d15?0 processor alternate bus master processor erwb aoeb coeb doeb rmcb siz1?iz0 tscae f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation motorola ec000 core processor user? manual 3-25 figure 3-20. 3-wire bus arbitration timing diagram?us inactive s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 clki bgackb negated bgb asserted and bus three stated brb valid internal brb sampled brb asserted brb bgb bgackb fc2?c0 a31?0 asb ud sb and/or ldsb dsb rwb dtackb d15?0 bus released from three state and processor starts next bus cycle processor processor bus inactive alternate bus master erwb aoeb coeb doeb rmcb siz1?iz0 tscae f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation 3-26 ec000 core processor user? manual motorola figure 3-21. 3-wire bus arbitration timing diagram?pecial case bus three-stated bgb asserted brb valid internal brb sampled brb asserted bus released from three state and processor starts next bus cycle bgackb negated internal bgackb sampled bgackb negated brb bgb bgackb asb udsb and/or ldsb dsb rwb dtackb d15?0 s0 s2 s4 s6 s0 s2 s4 s6 s0 clki fc2?c0 a31?0 erwb processor alternate bus master processor aoeb coeb doeb rmcb siz1?iz0 tscae f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation motorola ec000 core processor user? manual 3-27 figure 3-22. 2-wire bus arbitration timing diagram?cm68000 active s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 s5 s6 s7 s0 s 1 clki bus three-stated bgb asserted brb valid internal brb sampled brb asserted bus released from three state and processor starts next bus cycle brb negated internal brb sampled brb negated brb bgb bgackb fc2?c0 a31?0 asb u dsb and/or lsdb dsb rwb dtackb d15?0 processor alternate bus master processor erwb aoeb coeb doeb rmcb siz1?iz0 tscae f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation 3-28 ec000 core processor user? manual motorola figure 3-23. 2-wire bus arbitration timing diagram?us inactive s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 clki brb negated bgb asserted and bus three stated brb valid internal brb sampled brb asserted brb bgb bgackb bus released from three state and processor starts next bus cycle fc2?c0 a31?0 asb u dsb and/or ldsb dsb rwb dtackb d15?0 processor processor bus inactive alternate bus master erwb aoeb coeb doeb rmcb siz1?iz0 tscae f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation motorola ec000 core processor user? manual 3-29 figure 3-24. 2-wire bus arbitration timing diagram?pecial case bus three-stated bgb asserted brb valid internal brb sampled brb asserted bus released from three state and processor starts next bus cycle brb negated internal brb sampled brb negated brb bgb bgackb s0 s2 s4 s6 s0 s2 s4 s6 s0 clki asb udsb and/or ldsb dsb rwb dtackb d15?0 fc2?c0 a31?0 erwb processor alternate bus master processor aoeb coeb doeb rmcb siz1?iz0 tscae f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation 3-30 ec000 core processor user? manual motorola 3.4 bus error and halt operation in a bus architecture that requires a handshake from an external device, such as the asyn- chronous bus used in the scm68000, the handshake may not always occur. a bus error input is provided to terminate a bus cycle in error when the expected signal is not asserted. different systems and different devices within the same system require different maximum response times. external circuitry can be provided to assert the bus error signal after the appropriate delay following the assertion of address strobe. 3.4.1 bus error operation a bus error is recognized when haltib is negated and berrb is asserted, either alone or with dtackb. when the bus error condition is recognized, the current bus cycle is terminated in state 9 (s9) (only berrb is asserted) or in state 7 (s7) (berrb and dtackb are asserted) for a read cycle or a write cycle. the bus cycle is terminated in state 11 (s11) for the read portion of a read-modify-write cycle. for the write portion of a read-modify-write cycle, the bus cycle is terminated in state 21 (s21) (only berrb is asserted) or in state 19 (s19) (berrb and dtackb are asserted). as long as berrb remains asserted, the data bus is in the high- impedance state. figure 3-25 shows the timing for the normal bus error. after the aborted bus cycle is terminated and berrb is negated, the scm68000 enters ex- ception processing for the bus error exception. during the exception processing sequence, the following information is placed on the supervisor stack: 1. status register 2. program counter (two words, which may be up to five words past the instruction being executed) 3. error information the first two items are identical to the information stacked by any other exception. the scm68000 stacks bus error information to help determine and to correct the error. after the scm68000 has placed the required information on the stack, the bus error excep- tion vector is read from vector table entry 2 (offset $08) and placed in the program counter. the scm68000 resumes execution at the address in the vector, which is the first instruction in the bus error handler routine. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation motorola ec000 core processor user? manual 3-31 figure 3-25. bus error timing diagram s0 s2 s4 s6 clki fc2?c0 a31?0 ww ww s8 asb udsb and/or ldsb rwb dtackb d15?0 berrb haltib initiate bus error detection initiate bus error stacking response failure read dsb erwb aoeb coeb doeb rmcb siz1?iz0 tscae f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation 3-32 ec000 core processor user? manual motorola 3.4.2 retrying the bus cycle the assertion of berrb during a bus cycle in which haltib is also asserted by an external device initiates a retry operation. figure 3-26 is a timing diagram of the retry operation. the scm68000 terminates the bus cycle, then puts the data bus in the high-impedance state. the scm68000 remains in this state until haltib is negated. then the scm68000 retries the preceding cycle using the same function codes, address, and data (for a write operation). berrb should be negated at least one clock cycle before haltib is negated. note to guarantee that the entire read-modify-write cycle runs cor- rectly and that the write portion of the operation is performed without negating the address strobe, the scm68000 does not retry a read-modify-write cycle. when berrb is asserted during a read-modify-write operation, a bus error operation is per- formed whether or not haltib is asserted. 3.4.3 halt operation haltib performs a halt/run/single-step operation similar to the halt operation of an mc68000. when haltib is asserted by an external device, the scm68000 halts and remains halted as long as the signal remains asserted, as shown in figure 3-27. while the scm68000 is halted, only the data bus is placed in the high-impedance state as shown in table 2-1. bus arbitration is performed as usual. should a bus error occur while haltib is asserted, the scm68000 performs the retry operation previously described. the single-step mode is derived from correctly timed transitions of haltib. haltib is negated to allow the scm68000 to begin a bus cycle, then asserted to enter the halt mode when the cycle completes. the single-step mode proceeds through a program one bus cycle at a time for debugging purposes. the halt operation and the hardware trace capability allow tracing of either bus cycles or instructions one at a time. these capabilities and a software debugging package provide total debugging flexibility. note execution of the reset instruction while using the haltib sig- nal in the single-step mode can cause the scm68000 to reset. 4.3.1 reset has more detailed information about the reset in- struction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation motorola ec000 core processor user? manual 3-33 figure 3-26. retry bus cycle timing diagram s0 s2 s4 s6 clki fc2?c0 a31?0 s8 s0 s2 s4 s6 asb udsb and/or ldsb rwb dtackb d15?0 berrb haltib 1 clock period read halt retry dsb erwb aoeb coeb doeb rmcb siz1?iz0 tscae 3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation 3-34 ec000 core processor user? manual motorola figure 3-27. halt operation timing diagram s0 s2 s4 s6 clki fc2?c0 a31?0 s0 s2 s4 s6 asb rwb dtackb d15?0 haltib udsb and/or ldsb read halt read dsb erwb aoeb coeb doeb rmcb siz1?iz0 tscae f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation motorola ec000 core processor user? manual 3-35 3.4.4 double bus fault when a bus error exception occurs, the scm68000 begins exception processing by stack- ing information on the supervisor stack. if another bus error occurs during exception pro- cessing (i.e., before execution of another instruction begins) the scm68000 halts and asserts haltob. this situation is a double bus fault. only an external reset operation can restart a scm68000 halted due to a double bus fault. a retry operation does not initiate exception processing; a bus error during a retry operation does not cause a double bus fault. the scm68000 can continue to retry a bus cycle indef- initely if external hardware requests. a double bus fault occurs during a reset operation when a bus error occurs while the scm68000 is reading the vector table (before the first instruction is executed). the reset operation is described in 4.3.1 reset . 3.5 asynchronous operation all asynchronous input signals to the scm68000 are synchronized before being used inter- nally. as shown in figure 3-28, synchronization requires a maximum of one cycle of the sys- tem clock, assuming that the asynchronous input setup time (spec #47, defined in section 7 electrical characteristics ) has been met. the input asynchronous signal is sampled on the falling edge of the clock and is valid internally after the next rising edge. the asynchro- nous inputs are avecb, resetib, haltib, dtackb, berrb, iplb2?plb0, brb, and bgackb. figure 3-28. external asynchronous signal synchronization clki brb (external) brb (internal) 47 internal signal valid external signal sampled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation 3-36 ec000 core processor user? manual motorola to achieve clock frequency independence at a system level, the bus can be operated in an asynchronous manner. asynchronous bus operation uses the bus handshake signals to control the transfer of data. the handshake signals are asb, udsb, ldsb, dsb, dtackb, berrb, haltib, and avecb. asb indicates the start of the bus cycle, and udsb, ldsb, and dsb signal valid data for a write cycle. after placing the requested data on the data bus (read cycle) or latching the data (write cycle), the slave device (memory or peripheral) asserts dtackb to terminate the bus cycle. if no device responds or if the access is invalid, external control logic asserts berrb, or berrb and haltib, to abort or retry the cycle. figure 3-29 shows the use of the bus handshake signals in a fully asynchronous read cycle. figure 3-30 shows a fully asynchronous write cycle. in the asynchronous mode, the accessed device operates independently of the frequency and phase of the system clock. for example, the mc68681 dual universal asynchronous receiver/transmitter (duart) does not require any clock-related information from the bus master during a bus transfer. asynchronous devices are designed to operate correctly with processors at any clock frequency when relevant timing requirements are observed. figure 3-29. fully asynchronous read cycle figure 3-30. fully asynchronous write cycle asb rwb dtackb udsb and/or ldsb d15?0 a31?0 and dsb a31?0 asb rwb udsb and/or ldsb d15?0 dtackb and dsb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation motorola ec000 core processor user? manual 3-37 a device can use a clock at the same frequency as the system clock, but without a defined phase relationship to the system clock. this mode of operation is pseudo-asynchronous; it increases performance by observing timing parameters related to the system clock fre- quency without being completely synchronous with that clock. a common example of a pseudo-asynchronous device is a memory array designed to operate with the scm68000 at a certain frequency but is not driven by the scm68000 clock. the designer of a fully asynchronous system can make no assumptions about address setup time, which could be used to improve performance. however, with the system clock frequency known, the slave device can be designed to decode the address bus before rec- ognizing an address strobe. parameter #11 (refer to section 7 electrical characteristics for all parameters listed in this section) specifies the minimum time before address strobe during which the address is valid. in a pseudo-asynchronous system, timing specifications allow dtackb to be asserted for a read cycle (see figure 3-31) before the data from a slave device is valid. the length of time that dtackb may precede data is specified as parameter #31 in figure 3-31. this parameter must be met to ensure the validity of the data latched into the scm68000. no maximum time is specified from the assertion of asb to the assertion of dtackb. during this unlimited time, the scm68000 inserts wait cycles in one-clock-period increments until dtackb is recognized. figure 3-31 shows the important timing parameters for a pseudo- asynchronous read cycle. during a write cycle (see figure 3-32), after the scm68000 asserts asb but before driving the data bus, the scm68000 drives rwb to a logic low. parameter #55 specifies the mini- figure 3-31. pseudo-asynchronous read cycle a31?0 asb rwb data dtackb 17 31 29 15 13 udsb and/or ldsb and dsb 11 28 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation 3-38 ec000 core processor user? manual motorola mum time between the transition of rwb and the driving of the data bus, which is effectively the maximum turnoff time for any device driving the data bus. after the scm68000 places valid data on the bus, it asserts the data strobe signals. a data setup time, similar to the address setup time previously discussed, can be used to improve performance. parameter #26 is the minimum time a slave device can accept valid data before recognizing a data strobe. the slave device asserts dtackb after it accepts the data. parameter #25 is the minimum time after negation of the strobes during which the valid data remains on the address bus. parameter #28 is the maximum time between the nega- tion of the strobes by the scm68000 and the negation of dtackb by the slave device. if dtackb remains asserted past the time specified by parameter #28, the scm68000 may recognize it as being asserted early in the next bus cycle and may terminate that cycle pre- maturely. figure 3-32 shows the important timing parameters for a pseudo-asynchronous write cycle. 3.6 synchronous operation in some systems, external devices use the system clock to generate dtackb and other asynchronous input signals. this synchronous operation provides a closely coupled design with maximum performance, appropriate for frequently accessed parts of the system. for example, memory can operate in the synchronous mode, but peripheral devices operate asynchronously. for a synchronous device, the designer uses explicit timing information shown in section 7 electrical characteristics . these specifications define the state of all bus signals relative to a specific state of the scm68000 clock. the standard scm68000 bus cycle consists of four clock periods (eight bus cycle states) and, optionally, an integral number of clock cycles inserted as wait states. wait states are figure 3-32. pseudo-asynchronous write cycle a31?0 asb rwb udsb and/or ldsb d15?0 dtackb 11 55 22 26 28 25 20a 13 17 and dsb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation motorola ec000 core processor user? manual 3-39 inserted as required to allow sufficient response time for the external device. the following state-by-state description of the bus cycle differs from those descriptions in 3.1.1 read cycle and 3.1.2 write cycle by including information about the important timing parameters that apply in the bus cycle states. figure 3-33 shows a synchronous read cycle and the important timing parameters that apply. the timing for a synchronous write cycle, including relevant timing parameters, is shown in figure 3-34. state 0 the bus cycle starts in s0, during which the clock is high. at the rising edge of s0, the function code for the access is driven externally. parameter #6a defines the delay from this rising edge until the function codes are valid. the address of the accessed device is driven externally with an assertion delay defined by parameter #6. the rwb and erwb signals are driven to logic high; parameter #18 defines the delay from the same rising edge to the transition of rwb. the minimum value for parameter #18 applies to a read figure 3-33. synchronous read cycle a31?0 udsb and/or ldsb rwb asb clki dtackb 9 s0 s1 s2 s3 s4 s5 s6 s7 s0 18 47 27 d15?0 6a fc2?c0 and dsb 29 28 12 erwb 6 28 47 c6 tscae f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation 3-40 ec000 core processor user? manual motorola cycle preceded by a write cycle; this value is the maximum hold time for a logic low on rwb beyond the initiation of the read cycle. the tscae signal is driven to a logic high. parameter #c6 defines the delay from the rising edge of the clock to the assertion of tscae. state 1 entering s1, a low period of the clock, tscae is driven to a logic low. during a write, the erwb signal is driven to a logic low with an assertion delay defined by parameter #c3. state 2 on the rising edge of s2, a high period of the clock, asb is asserted. during a read cycle, udsb, ldsb, and dsb are also asserted at this time. parameter #9 defines the assertion delay for these signals. for a write cycle, the rwb signal is driven to a logic low with a delay defined by parameter #20. figure 3-34. synchronous write cycle a31?0 udsb and/or ldsb rwb asb clki dtackb 6 9 9 s0 s1 s2 s3 s4 s5 s6 s7 s0 18 47 d15?0 6a fc2?c0 and dsb 28 12 20 23 53 erwb tscae c6 c3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation motorola ec000 core processor user? manual 3-41 state 3 on the falling edge of the clock entering s3 during a write cycle, the data bus is driven out of the high-impedance state with the data being written to the accessed device. parameter #23 specifies the data assertion delay. in a read cycle, no signal is altered in s3. state 4 entering the high clock period of s4 during a write cycle, udsb, ldsb, and dsb are as- serted on the rising edge of the clock. as in s2 for a read cycle, parameter #9 defines the assertion delay from the rising edge of s4 for udsb, ldsb, and dsb. in a read cycle, no signal is altered by the scm68000 during s4. until the falling edge of the clock at the end of s4 (beginning of s5), no response from any external device except resetib is acknowledged by the scm68000. if either dtackb or berrb is asserted before the falling edge of s4 and satisfies the input setup time de- fined by parameter #47, the scm68000 enters s5 and the bus cycle continues. if either dtackb or berrb is asserted but without meeting the setup time defined by parameter #47, the scm68000 may recognize the signal and continue the bus cycle; the result is un- predictable. if neither dtackb nor berrb is asserted before the next falling edge of the clock, the bus cycle remains in s4, and wait states (complete clock cycles) are inserted until one of the bus cycle termination conditions is met. state 5 s5 is a low period of the clock, during which the scm68000 does not alter any signal. state 6 s6 is a high period of the clock, during which data for a read operation is set up relative to the falling edge (entering s7). parameter #27 defines the minimum period by which the data must precede the falling edge. for a write operation, the scm68000 changes no sig- nal during s6. state 7 on the falling edge of the clock entering s7, the scm68000 latches data and negates asb and udsb, ldsb, and dsb during a read cycle. the hold time for these strobes from this falling edge is specified by parameter #12. the hold time for data relative to the ne- gation of asb and udsb, ldsb, and dsb is specified by parameter #29. for a write cy- cle, only asb and udsb, ldsb, and dsb are negated; timing parameter #12 also applies. during a write cycle, on the rising edge of the clock at the end of s7 (which may be the start of s0 for the next bus cycle), the scm68000 also places the data bus in the high- impedance state and drives rwb and erwb to a logic high. external logic circuitry should respond to the negation of the asb and udsb, ldsb, and dsb by negating dtackb and/or berrb. parameter #28 is the hold time for dtackb, and parameter #30 is the hold time for berrb. a key consideration when designing in a synchronous environment is the timing for the assertion of dtackb and berrb by an external device. to properly use external inputs, the scm68000 must synchronize these signals to the internal clock. the scm68000 must sample the external signal and determine whether to consider it high or low during the suc- f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation 3-42 ec000 core processor user? manual motorola ceeding clock period. the external signal has no defined phase relationship to the cpu clock and may be changing at sampling time. successful synchronization requires that the internal machine receives a valid logic level (not a metastable signal), whether the input is high, low, or in transition. metastable signals propagating through synchronous machines can produce unpredictable operation. parameter #47 of section 7 electrical characteristics is the asynchronous input setup time. signals that meet parameter #47 are guaranteed to be recognized at the next falling edge of the system clock. however, signals that do not meet parameter #47 are not guar- anteed to be recognized. in addition, if dtackb is recognized on a falling edge, valid data is latched into the scm68000 (during a read cycle) on the next falling edge, provided the data meets the setup time required (parameter #27). when parameter #27 has been met, parameter #31 may be ignored. if dtackb is asserted with the required setup time before the falling edge of s4, no wait states are incurred, and the bus cycle runs at its maximum speed of four clock periods. 3.7 the relationship of dtackb, berrb, and haltib to properly control termination of a bus cycle for a retry or a bus error condition, dtackb, berrb, and haltib should meet the setup and hold time to the falling edge of the scm68000 clock. specification #48 (see section 7 electrical characteristics ), can be ignored when dtackb, berrb, and haltib are stable at the falling edge of the scm68000 clock. the possible bus cycle termination can be summarized as follows (case numbers refer to table 3-1): normal termination?tackb is asserted. berrb and haltib remain negated (case 1). halt termination?altib is asserted coincident with or preceding dtackb, and berrb remains negated (case 2). bus error termination?errb is asserted in lieu of, coincident with, or preceding dtackb (case 3). haltib remains negated, and berrb is negated coincident with or after dtackb. retry termination?altib and berrb are asserted in lieu of, coincident with, or be- fore dtackb (cases 4, 5, and 6). berrb is negated coincident with or after dtackb. haltib must be held at least one cycle after berrb. table 3-1 shows the details of the resulting bus cycle termination for various combinations of signal sequences. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation motorola ec000 core processor user? manual 3-43 the negation of berrb and haltib under several conditions is shown in table 3-2. dtackb is assumed to be negated normally in all cases. for reliable operation, both dtackb and berrb should be negated when address strobe is negated. table 3-2 shows when berrb and haltib should be negated with respect to when they were asserted to produce various results. the first column describes which case in table 3- 1 is being used for asserting the signals. the third column shows the current bus state and the fourth column shows the following bus state. the last column describes what will happen in the next bus cycle given the conditions described in the previous columns. table 3-1. dtackb, berrb, and haltib assertion results case no. control signal input asserted on rising edge of state * result n n+2 1 dtackb berrb haltib a na na s x x normal cycle terminate and continue. 2 dtackb berrb haltib a na a/s s x s normal cycle terminate and halt. continue when haltib negated. 3 dtackb berrb haltib x a na x s na terminate and take bus error trap. 4 dtackb berrb haltib na a na x s a terminate and retry when haltib negated. 5 dtackb berrb haltib x a a x s s terminate and retry when haltib negated. 6 dtackb berrb haltib na na a x a s terminate and retry when haltib negated. legend: n the number of the current even bus state (e.g., s4, s6, etc.) a signal asserted in this bus state na signal not asserted in this bus state x don't care s signal asserted in preceding bus state and remains asserted in this state * the dtackb, berrb, and haltib signals are subject to the setup and hold time (spec #47, defined in section 7 electrical characteristics ) before they are sampled on the falling edge of the previous state. ?sserted?in this table refers to the time when the sig- nals are valid internally. see 3.5 asynchronous operation for more details on external asynchronous signal synchronization. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
bus operation 3-44 ec000 core processor user? manual motorola example a: a system uses a watchdog timer to terminate accesses to unused address space. the timer asserts berrb after timeout (case 3). example b: a system uses error detection on random-access memory (ram) contents. the system de- signer may: 1. delay dtackb until the data is verified. if data is invalid, return berrb and haltib simultaneously to retry the error cycle (case 5). 2. delay dtackb until the data is verified. if data is invalid, return berrb at the same time as dtackb to take a bus error trap (case 3). table 3-2. berrb and haltib negation results conditions of termination in table 3-1 control signal input negated on rising edge of state * results?ext cycle n n+2 normal (cases 1 and 2) berrb haltib may lengthen next cycle. normal (cases 1 and 2) berrb haltib may lengthen next cycle. normal (cases 1 and 2) berrb haltib if next cycle is started, it will be terminated as a bus error. normal (cases 1 and 2) berrb haltib none if next cycle is started, it will be terminated as a bus error. bus error (case 3) berrb haltib none takes bus error trap. rerun (cases 4, 5, and 6) berrb haltib illegal sequence; usually traps to vector number 0. rerun (cases 4, 5, and 6) berrb haltib illegal sequence; usually traps to vector number 0. rerun (cases 4, 5, and 6) berrb haltib reruns the bus cycle. legend: n the number of the current even bus state (e.g., s4, s6, etc.) signal is negated in this bus state. none signal was not asserted. *the berrb and haltib signals are subject to the setup and hold time (spec #47, de?ed in section 7 electrical characteristics ) before they are sampled on the falling edge of the previous state. ?egated?in this table refers to the time when the signals are valid internally. see 3.5 asynchronous operation for more details on the external asynchronous signal synchronization. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola ec000 core processor user? manual 4-1 section 4 exception processing this section describes operations of the scm68000 (ec000 core) 1 outside the normal pro- cessing associated with the execution of instructions. the functions of the bits in the super- visor portion of the status register are described: the supervisor/user bit, the trace enable bit, and the interrupt priority mask. finally, the sequence of memory references and actions taken by the scm68000 for exception conditions are described in detail. the scm68000 is always in one of three processing states: normal, exception, or halted. the normal processing state is associated with instruction execution; the memory refer- ences are to fetch instructions and operands and to store results. a special case of the nor- mal state is the stopped state, resulting from the execution of a stop instruction. in this state, no further memory references are made. the exception processing state is associated with interrupts, trap instructions, tracing, and other exceptional conditions. the exception may be internally generated by an instruction or by an unusual condition arising during the execution of an instruction. externally, exception processing can be forced by an interrupt, a bus error, or a reset. exception processing pro- vides an efficient context switch so that the scm68000 can handle unusual conditions. the halted processing state is an indication of catastrophic hardware failure. for example, if during the exception processing of a bus error another bus error occurs, the scm68000 assumes the system is unusable and halts. only an external reset can restart the halted scm68000. note that the stopped state is not the same as the halted state. 4.1 privilege modes the scm68000 operates in one of two levels of privilege: the supervisor mode or the user mode. the privilege mode determines which operations are legal. the mode is optionally used by an external memory management device to control and translate accesses. the mode is also used to choose between the supervisor stack pointer (ssp) and the user stack pointer (usp) in instruction references. the privilege mode is a mechanism for providing security in a computer system. programs should access only their own code and data areas and should be restricted from accessing information that they do not need and must not modify. the operating system executes in the supervisor mode, allowing it to access all resources required to perform the overhead tasks for the user mode programs. most programs execute in user mode, in which the accesses are controlled and the effects on other parts of the system are limited. 1. the scm68000 is the name of the verilog model for the ec000 core. the remainder of this section will refer to the part as only the scm68000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing 4-2 ec000 core processor user? manual motorola 4.1.1 supervisor mode the supervisor mode has the higher level of privilege. the mode of the scm68000 is deter- mined by the s-bit of the status register; if the s-bit is set, the scm68000 is in the supervisor mode. all instructions can be executed in the supervisor mode. the bus cycles generated by instructions executed in the supervisor mode are classified as supervisor references. while the scm68000 is in the supervisor mode, those instructions that use either the system stack pointer implicitly or address register seven explicitly access the ssp. 4.1.2 user mode the user mode has the lower level of privilege. if the s-bit of the status register is clear, the scm68000 is executing instructions in the user mode. most instructions execute identically in either mode. however, some instructions having important system effects are designated privileged. for example, user programs are not permitted to execute the stop instruction or the reset instruction. to ensure that a user program cannot enter the supervisor mode except in a controlled manner, the instructions that modify the entire status register are privileged. to aid in debugging system software, the move to user stack pointer (move to usp) and move from user stack pointer (move from usp) instructions are privileged. the bus cycles generated by an instruction executed in user mode are classified as user references. classifying a bus cycle as a user reference allows an external memory manage- ment device to control access to protected portions of the address space. while the scm68000 is in the user mode, those instructions that use either the system stack pointer implicitly or address register seven explicitly access the usp. 4.1.3 privilege mode changes the transition from supervisor to user mode can be accomplished by any of four instructions: return from exception (rte), move to status register (move to sr), and immediate to sta- tus register (andi to sr), and exclusive or immediate to status register (eori to sr). the rte instruction fetches the new status register and program counter from the supervisor stack and loads each into its respective register. next, it begins the instruction fetch at the new program counter address in the privilege mode determined by the s-bit of the new con- tents of the status register. once the scm68000 is in the user mode and is executing instructions, only exception pro- cessing can change the privilege mode. during exception processing, the current state of the s-bit of the status register is saved, and the s-bit is set, putting the scm68000 in the supervisor mode. therefore, when instruction execution resumes at the address specified to process the exception, the scm68000 is in the supervisor privilege mode. the move to sr, andi to sr, and eori to sr instructions fetch all operands in the super- visor mode, perform the appropriate update to the status register, and then fetch the next instruction at the next sequential program counter address in the privilege mode determined by the new s-bit. the instruction following the move/andi/eori sr instruction will be fetched twice, once from the old fc space and again from the new fc space (even if the s- f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing motorola ec000 core processor user? manual 4-3 bit was not modified). external memory management hardware should not treat the access in the old fc space as an error. 4.1.4 reference classification when the scm68000 makes a reference, it classifies the reference according to the encod- ing of the three function code output lines. this classification allows external translation of addresses, control of access, and differentiation of special scm68000 states, such as cpu space (used by interrupt acknowledge cycles). table 4-1 lists the classification of refer- ences. 4.1.5 cpu space cycle a cpu space cycle, indicated when the function codes are all high, is a special cycle. bits a19?16 of the address bus identify sixteen types of cpu space cycles. the interrupt acknowledge cycle, in which a19?16 are high, is currently the only defined cpu space cycle for the scm68000. other configurations of a19?16 are reserved by motorola to define other types of cpu cycles used in other m68000 family microprocessors. figure 4- 1 shows the encoding of cpu space addresses. 4.1.5.1 interrupt acknowledge cycle. the interrupt acknowledge cycle places the level of the interrupt being acknowledged on address bits a3?1 and drives all other ad- dress lines high. for a vectored interrupt, the interrupt acknowledge cycle reads a vector number when the interrupting device places a vector number on the data bus and asserts dtackb to acknowledge the cycle. the timing diagram for a vectored interrupt is shown in figure 4-2. table 4-1. reference classification function code output address space fc2 fc1 fc0 0 0 0 (reserved) * 0 0 1 user data 0 1 0 user program 0 1 1 (undefined) * 1 0 0 (reserved) * 1 0 1 supervisor data 1 1 0 supervisor program 1 1 1 cpu space * address space 3 is reserved for user de?ition, while 0 and 4 are reserved for future use by motorola. figure 4-1. cpu space address encoding 1111111111111111111111111111 11 1 interrupt acknowledge function code 2 0 31 19 16 0 cpu space type field level 1 31 address bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing 4-4 ec000 core processor user? manual motorola figure 4-2. interrupt acknowledge cycle timing diagram (sheet 1 of 3) clki fc2?c0 a31?4 asb udsb ldsb rwb dtackb d15?8 d7?0 iplb2?plb0 a3?1 last bus cycle of instruction (read or write) s0 s1 s2 s3 s4 s5 s6 s7 iplb2?plb0 transition iplb2?plb0 sampled iplb2?plb0 valid internally a0 erwb doeb aoeb coeb rmcb siz1?iz0 tscae internal operations dsb stack low word of pc on ssp s0 s1 s7 s0 s1 s2 s3 s4 s5 s6 fcx = $5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing motorola ec000 core processor user? manual 4-5 figure 4-2. interrupt acknowledge cycle timing diagram (sheet 2 of 3) clki fc2?c0 a31?4 asb udsb ldsb dsb rwb dtackb d15?8 d7?0 iplb2?plb0 a3?1 a0 erwb doeb aoeb coeb rmcb siz1?iz0 tscae *during an iack cycle, although a vector number is one byte, both data strobes are asserted due to the microcode used for exception processing. the processor does not recognize anything on d15?8 at this time. iack cycle* stack status register on ssp s0 s1 s2 s3 s4 s5 s6 s7 s7 s0 s1 s2 s3 s4 s5 s6 s7 stack upper word of pc on ssp s7 s0 s1 s2 s3 s4 s5 s6 justify vector number acquisition s0 fcx = $5 fcx = $5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing 4-6 ec000 core processor user? manual motorola figure 4-2. interrupt acknowledge cycle timing diagram (sheet 3 of 3) clki fc2?c0 a31?4 asb udsb ldsb rwb dtackb d15?8 d7?0 iplb2?plb0 a3?1 a0 erwb doeb aoeb coeb rmcb siz1?iz0 tscae dsb read upper word of exception vector s7 s6 s7 s0 s1 s2 s3 s4 s5 s6 read lower word of exception vector resume instruction execution in interrupt handler s7 s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 s5 s6 fcx = $5 fcx = $5 fcx = $6 exception vector f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing motorola ec000 core processor user? manual 4-7 although the timing diagram in figure 4-2 is for the 16-bit mode, the following list describes the sequence of events executed by the processor for a vectored and autovectored interrupt in either mode. 1. make an internal copy of the current status register. 2. in the status register, set the s bit, clear the t bit, and replace the interrupt mask with the level of the interrupt that was recognized. no bus activity occurs during the six clocks required to complete steps 1 and 2. 3. stack the lower word of the program counter on the supervisor stack. 4. run an interrupt acknowledge bus cycle for vector number acquisition. this step takes four clock cycles with no wait states. for an autovectored interrupt, this step takes ten to eighteen clock cycles. 5. justify the vector number for vector acquisition. no bus activity occurs during the four clock periods that are required for this step. 6. stack the status register that was saved in step 1 on the supervisor stack. 7. stack the upper word of the program counter on the supervisor stack. 8. read the upper word of the exception vector. 9. read the lower word of the exception vector. 10. fetch the first word of the first instruction of the interrupt handler routine. 11. continue fetching instructions and executing as normal until the interrupt handling rou- tine is complete. 4.1.5.2 autovectored interrupt acknowledge cycle. an interrupt acknowl- edge cycle can be autovectored if avecb is asserted instead of dtackb in state 4 (s4). for an autovectored interrupt, the vector number is internally generated to be $18 plus the interrupt level. the autovector capability provides vectors for each of the six maskable inter- rupt levels and for the nonmaskable interrupt level. the timing diagram for an autovectored interrupt acknowledge cycle is shown in figure 4-3. after recognizing avecb, the processor waits until the test clock (testclk) signal is low. figure 4-4 shows the best-case timing of an autovectored interrupt acknowledge cycle, while figure 4-5 shows the worst-case timing. the cycle length is entirely dependent on the relationship of the assertion of avecb to the test clock. when avecb is recognized on the falling edge of s4 no extra wait states are inserted. the only wait states inserted are those required to synchronize avecb with the test clock. the synchronization delay is an integral number of system clock cycles within the following ex- tremes: 1. best case?he assertion of avecb is recognized on the falling edge of the system clock that occurs three clock cycles before testclk rises (or three clock cycles after testclk falls). 2. worst case?he assertion of avecb is recognized on the falling edge of the system clock that occurs two clock cycles before testclk rises (or four clock cycles after testclk falls). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing 4-8 ec000 core processor user? manual motorola the bus cycle ends in s7 when the scm68000 negates the address and data strobes, and the test clock goes low. the avecb signal must be removed within one clock cycle after the negation of address strobe. data transfer acknowledge (dtackb) must not be asserted while avecb is asserted. the state machine in the processor looks for dtackb to identify an asynchronous bus cycle and figure 4-3. autovector operation timing diagram avecb fc2?c0 clki a3?1 asb d15?8 s6 s0 s2 s0 s2 s4 s4 s6 s6 s8 s12 s16 s20 a31?4 udsb ldsb rwb dtackb d7?0 iplb2?plb0 dsb erwb stack low word of pc on ssp autovector * operation although both udsb and ldsb are asserted, no data is read from the bus during the autovector cycle. the vector number is generated internally. an autovector operation will take between 10 and 18 clock cycles. see the best and worst case examples on the following pages. note: * a0 doeb aoeb coeb rmcb siz1?iz0 tscae f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing motorola ec000 core processor user? manual 4-9 for avecb to identify an autovectored interrupt acknowledge cycle. if both signals are asserted, the operation of the state machine is unpredictable. figure 4-4. autovector operation timing diagram?est case s0 s2 clki s4 s6 s8 s10 s12 s14 s16 s18 fc2?c0 a3?1 siz1?iz0 a31?4 a0 dtackb rwb erwb rmcb doeb aoeb coeb data out data in testclk avecb asb ldsb udsb dsb tscae although both udsb and ldsb are asserted, no data is read from the bus during the autovector cycle. the vector number is generated internally. note: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing 4-10 ec000 core processor user? manual motorola figure 4-5. autovector operation timing diagram?orst case data out data in avecb s0 s2 s4 clki s36 s32 s28 s24 s20 s16 s12 s8 s6 fc2?c0 a3?1 asb testclk a31?4 a0 ldsb udsb dsb siz1?iz0 dtackb rwb erwb rmcb doeb aoeb coeb tscae although both udsb and ldsb are asserted, no data is read from the bus during the autovector cycle. the vector number is generated internally. note: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing motorola ec000 core processor user? manual 4-11 4.2 exception processing description the processing of an exception occurs in four steps, with variations for different exception causes: 1. make a temporary copy of the status register and set the status register for exception processing. 2. obtain the exception vector. 3. save the current scm68000 context. 4. obtain a new context and resume instruction processing. 4.2.1 exception vectors an exception vector is a memory location from which the scm68000 fetches the address of a routine to handle an exception. each exception type requires a handler routine and a unique vector. all exception vectors are two words in length (see figure 4-6) and reside in the supervisor data space, except for the reset vector, which is four words long and resides in the supervisor program space. a vector number is an 8-bit number that is multiplied by four to obtain the address of an exception vector. the scm68000 forms the vector address by left-shifting the vector num- ber two bit positions and zero-filling the upper-order bits to obtain a 32-bit long-word vector address (see figure 4-7). the vector numbers can be found in the vector table (see table 4-2) which is 512 words long (1024 bytes), starting at address 0 and proceeding through address 1023 (decimal). the vector table provides 255 unique vectors, some of which are reserved for trap and other sys- tem function vectors. of the 255 vectors, 192 are reserved for user interrupt vectors. how- ever, the first 64 entries are not protected, so user interrupt vectors may overlap at the discretion of the system designer. figure 4-6. exception vector format a31 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 all zeroes v7 v6 v5 v4 v3 v2 v1 v0 0 0 figure 4-7. address translated from 8-bit vector number new program counter (high) new program counter (low) a1 = 0 a1 = 1 word 0 word 1 even byte (a0 = 0) odd byte (a0 = 1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing 4-12 ec000 core processor user? manual motorola table 4-2. exception vector assignment vectors numbers address space 5 assignment hex decimal dec hex 0 0 0 000 sp reset: initial ssp 2 1 1 4 004 sp reset: initial pc 2 2 2 8 008 sd bus error 3 3 12 00c sd address error 4 4 16 010 sd illegal instruction 5 5 20 014 sd divide-by-zero 6 6 24 018 sd chk instruction 7 7 28 01c sd trapv instruction 8 8 32 020 sd privilege violation 9 9 36 024 sd trace a 10 40 028 sd line 1010 emulator b 11 44 02c sd line 1111 emulator c 12 1 48 030 sd (unassigned, reserved) d 13 1 52 034 sd (unassigned, reserved) e 14 1 56 038 sd (unassigned, reserved) f 15 60 03c sd uninitialized interrupt vector 10?7 16?3 1 64 040 sd (unassigned, reserved) 92 05c 18 24 96 060 sd spurious interrupt 3 19 25 100 064 sd level 1 interrupt autovector 1a 26 104 068 sd level 2 interrupt autovector 1b 27 108 06c sd level 3 interrupt autovector 1c 28 112 070 sd level 4 interrupt autovector 1d 29 116 074 sd level 5 interrupt autovector 1e 30 120 078 sd level 6 interrupt autovector 1f 31 124 07c sd level 7 interrupt autovector 20?f 32?7 128 080 sd trap instruction vectors 4 188 0bc 30?f 48?3 1 192 0c0 sd (unassigned, reserved) 255 0ff 40?f 64?55 256 100 sd user interrupt vectors 1020 3fc notes: 1.vector numbers 12?4, 16?3, and 48?3 are reserved for future enhancements by motorola. no user peripheral devices should be assigned these numbers. 2.reset vector (0) requires four words, unlike the other vectors which only require two words, and is located in the supervisor program space. 3.the spurious interrupt vector is taken when there is a bus error indication during interrupt processing. 4.trap #n uses vector number 32+ n (decimal). 5.sp denotes supervisor program space, and sd denotes supervisor data space. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing motorola ec000 core processor user? manual 4-13 4.2.2 kinds of exceptions exceptions are generated internally or externally, depending on the reason for the excep- tion. the external exceptions are generated by interrupts, bus errors, and a reset. the inter- rupts are requests from peripheral devices for scm68000 action. for interrupt requests, the peripheral must provide an 8-bit vector number on data bus lines d7-d0 (see figure 4-8). the bus error and reset inputs are used for access control and scm68000 restart. the internal exceptions are generated by instructions, address errors, or tracing. the trap (trap), trap on overflow (trapv), check register against bounds (chk), and divide (div) instructions can generate exceptions as part of their instruction execution. in addition, illegal instructions, word access to odd addresses, and privilege violations initiate exceptions. tracing is similar to a very high priority interrupt which is internally generated following each instruction. 4.2.3 multiple exceptions these paragraphs describe the processing that occurs when multiple exceptions arise simultaneously. exceptions can be grouped by their occurrence and priority. group 0 excep- tions are reset, bus error, and address error. these exceptions cause the instruction cur- rently being executed to abort and the exception processing to commence within two clock cycles. group 1 exceptions are trace and interrupt, privilege violations, and illegal instruc- tions. trace and interrupt exceptions allow the current instruction to execute to completion, but pre-empt the execution of the next instruction by forcing exception processing to occur. a privilege-violating instruction or an illegal instruction is detected when it is the next instruc- tion to be executed. group 2 exceptions occur as part of the normal processing of instruc- tions. trap, trapv, chk, and divide-by-zero exceptions are in this group. for these exceptions, normal execution of an instruction may lead to exception processing. group 0 exceptions have the highest priority and group 2 exceptions have the lowest prior- ity. within group 0, reset has the highest priority, followed by address error and then bus error. within group 1, trace has priority over external interrupts, which in turn takes priority over illegal instruction and privilege violation. since only one instruction can be executed at a time, no priority relationship applies within group 2. the priority relationship between two exceptions determines which is taken, or taken first, if the conditions for both arise simultaneously. therefore, if a bus error occurs during a trap instruction, the bus error takes precedence, and trap instruction processing is aborted. in another example, if an interrupt request occurs during the execution of an instruction while the t-bit is asserted, the trace exception has priority and is processed first. before instruc- tion execution resumes, however, the interrupt exception is also processed, and instruction d15 d8 d7 d6 d5 d4 d3 d2 d1 d0 ignored v7 v6 v5 v4 v3 v2 v1 v0 where v7 is the msb of the vector number and v0 is the lsb of the vector number. figure 4-8. interrupt vector number format f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing 4-14 ec000 core processor user? manual motorola processing finally commences in the interrupt handler routine. a summary of exception grouping and priority is given in table 4-3. as an example, consider trap, trace, and interrupt exceptions that occurred simultaneously and are pending. the exception processing for the trap occurs first, followed immediately by exception processing for the trace, and then for the interrupt. when the scm68000 resumes normal instruction execution, it is in the interrupt handler, which returns to the trace handler, which returns to the trap execution handler. the reset exception handler is always executed first because it clears all other exceptions. 4.2.4 exception stack frames exception processing saves the most volatile portion of the current scm68000 context on the top of the supervisor stack. this context is organized in a format called the exception stack frame. although this information varies with type of exception, it always includes the status register and program counter of the scm68000 when the exception occurred. the amount and type of information saved on the stack are determined by the exception type. exceptions are grouped by type according to priority of the exception. of the group 0 exceptions, the reset exception does not stack any information. the informa- tion stacked by a bus error or address error exception is described in 4.3.7 bus error and is shown in figure 4-14. the groups 1 and 2 exception stack frame is shown in figure 4-9. only the program counter and status register are saved. the program counter points to the next instruction to be exe- cuted after exception processing. 4.2.5 exception processing sequence in the first step of exception processing, an internal copy is made of the status register. after the copy is made, the s-bit of the status register is set, putting the scm68000 into the super- visor mode. also, the t-bit is cleared, which allows the exception handler to execute unhin- dered by tracing. for the reset and interrupt exceptions, the interrupt priority mask is also updated appropriately. in the second step, the vector number of the exception is determined. for interrupts, the vec- tor number is obtained by an scm68000 bus cycle classified as an interrupt acknowledge table 4-3. exception grouping and priority group exception processing 0 reset address error bus error exception processing begins as soon as the bus cycle is terminated 1 trace interrupt illegal privilege exception processing begins before the next instruction 2 trap, trapv chk divide-by-zero exception processing is started by normal instruction execution f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing motorola ec000 core processor user? manual 4-15 cycle. for all other exceptions, internal logic provides the vector number. this vector number is then used to calculate the address of the exception vector. the third step, except for the reset exception, is to save the current scm68000 status. (the reset exception does not save the context and skips this step.) the current program counter value and the saved copy of the status register are stacked using the ssp. the stacked pro- gram counter value usually points to the next unexecuted instruction. however, for bus error and address error, the value stacked for the program counter is unpredictable and may be incremented from the address of the instruction that caused the error. group 1 and 2 excep- tions use a short format exception stack frame. additional information defining the current context is stacked for the bus error and address error exceptions. the last step is the same for all exceptions. the new program counter value is fetched from the exception vector. the scm68000 then resumes instruction execution at the address provided by the exception vector, and normal instruction decoding and execution is started. 4.3 processing of specific exceptions the exceptions are classified according to their sources, and each type is processed differ- ently. the following paragraphs describe in detail the types of exceptions and the processing of each type. 4.3.1 reset the reset exception corresponds to the highest exception level. the processing of the reset exception is performed for system initiation and recovery from catastrophic failure. if the scm68000 is currently executing a bus cycle, it will start processing at state 5 (s5) imme- diately after the internal reset signal is valid. the bus cycle will end at state 7 (s7) and the current instruction being executed will be canceled. the scm68000 is forced into the super- visor state, and the trace state is forced off. the interrupt priority mask is set to level seven. the vector number is internally generated to reference the reset exception vector at location zero in the supervisor program space. because no assumptions can be made about the validity of register contents, in particular the ssp, neither the program counter nor the status register is saved. the address in the first two words of the reset exception vector is fetched as the initial ssp, and the address in the last two words of the reset exception vector is figure 4-9. groups 1 and 2 exception stack frame even byte odd byte program counter low program counter high ssp 7070 0 15 status register higher address f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing 4-16 ec000 core processor user? manual motorola fetched as the initial program counter. finally, instruction execution is started at the address in the program counter. the initial program counter should point to the power-up/restart code. the reset instruction does not cause a reset exception; it asserts the resetob signal to reset external devices, which allows the software to reset the system to a known state and continue processing with the next instruction. 4.3.1.1 reset operation. the scm68000 has an input reset signal (resetib) and an output reset signal (resetob). in many cases, these two signals are connected to form just one bi-directional resetb signal. one way of combining these signals using cells from the motorola standard cell library is illustrated in figure 4-10. the scm68000 and it? exter- nal circuitry can be reset in three ways: asserting resetib and haltib simultaneously, asserting only resetib, and using the reset instruction. the methods to reset the scm68000 and it? external devices are described in the following paragraphs. 4.3.1.1.1 reset using resetib and haltib. for the initial reset, resetib and haltib must be asserted by an external device for at least 132 clock periods. resetting the scm68000 initializes the internal state. the scm68000 reads the reset vector table entry (address $00000) and loads the contents into the ssp. next, the scm68000 loads the con- tents of address $00004 (vector table entry 1) into the program counter. then the scm68000 initializes the status registers by setting the supervisor state, clearing the trace mode bit, and setting the interrupt mask level to seven. no other register is affected by the reset sequence. the internal circuitry may cause the scm68000 to take up to four clock periods to recognize that a reset is taking place. the timings for the intial reset operation are shown in figure 4-11. subsequent resets can be accomplished by asserting resetib and haltib simulta- neously for ten or more clock periods. 4.3.1.1.2 reset instruction. the reset instruction causes the scm68000 to assert resetob for 124 clock periods to reset the external devices of the system. the internal state of the scm68000 is not affected. neither the status register nor any of the internal figure 4-10. reset circuit resetob resetib inbuf resetb iopd iobuf f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing motorola ec000 core processor user? manual 4-17 registers are affected by a reset instruction. figure 4-12 shows a timing diagram for resetob. note the user must ensure that all external devices are reset at the completion of the reset instruction. the resetob signal is negated on the rising edge of s0 of the next bus cycle. if the resetib and resetob signals are connected as shown in figure 4-10, the haltib signal should not be asserted during the reset instruction. when the scm68000 recog- nizes that both the haltib and resetib signals are asserted, it will begin the reset excep- tion and negate resetob which will cause resetib to be negated. since resetib would not be asserted for at least ten clock periods with haltib, a partial reset will occur and may drive the scm68000 into an unknown state. 4.3.1.1.3 reset using only resetib. the scm68000 must initially be reset using the resetib and haltib signals as previously described. however, subsequent resets can also be accomplished by asserting only the resetib signal for a minimum of 132 clock peri- ods. because an assertion of the resetib signal is ignored while the resetob signal is asserted, the two signals can be connected as shown in figure 4-10. since the core may be executing a reset instruction at the time it is being reset using only the resetib signal, the resetib signal should be asserted for a minimum of 132 clock periods. this will ensure that the resetob signal has been negated and the resetib signal will be recognized. figure 4-11. reset operation timing diagram t 4 clocks note 2 note 3 note 4 note 5 note 6 notes 1. internal start-up time 2. ssp high read in here 3. ssp low read in here 4. pc high read in here 5. pc low read in here 6. first instruction fetched here bus state unknown: all control signals inactive. all three-state signals in the high-impedance state. clki v cc resetib haltib bus cycles < t 132 clock periods note1 for 16-bit mode: v dd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing 4-18 ec000 core processor user? manual motorola 4.3.1.2 initializing the scm68000 for simulation. to simulate the scm68000 properly, the initialization procedure differs slightly from the actual part. this difference is necessary to correctly start the test clock (testclk). both haltib and resetib must be asserted for at least 10 clock cycles. the test signal must be asserted for at least two clock cycles while haltib and resetib are asserted and must be negated at least two clock cycles before haltib and resetib are negated. figure 4-13 shows the timing for initializ- ing the scm68000 for simulation. if the scm68000 has been properly reset during simulation, the testclk signal will pulse with a period equal to ten scm68000 clock periods. the period will consist of six scm68000 clock periods in the low position and four scm68000 clock periods in the high position. figure 4-12. resetob timing diagram clki fc2?c0 a31?0 asb udsb/ldsb rwb dtackb d15?0 resetob erwb doeb aoeb rmcb siz1?iz0 tscae dsb coeb s7 s0 s1 s2 s3 s4 s5 s6 reset instruction (132 clock cycles) 124 clock cycles s7 s4 s5 s6 s0 s1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing motorola ec000 core processor user? manual 4-19 4.3.2 interrupts seven levels of interrupt priorities are provided, numbered 1?. devices can be chained externally within interrupt priority levels, allowing an unlimited number of peripheral devices to interrupt the scm68000. the status register contains a 3-bit mask indicating the current interrupt priority, and interrupts are inhibited for all priority levels less than or equal to the current priority. an interrupt request is made to the scm68000 by encoding the interrupt request levels 1 7 on the three interrupt request lines (iplb2?plb0); all negated lines indicate no interrupt request. interrupt requests arriving at the scm68000 do not force immediate exception pro- cessing, but the requests are made pending. pending interrupts are detected between instruction executions. if the priority of the pending interrupt is lower than or equal to the cur- rent scm68000 priority, execution continues with the next instruction, and the requesting interrupt is postponed until the priority of the pending interrupt becomes greater than the cur- rent scm68000 priority. if the priority of the pending interrupt is greater than the current scm68000 priority, the exception processing sequence for the requesting interrupt is started. a copy of the status register is saved; the privilege mode is set to supervisor mode; tracing is suppressed; and the scm68000 priority level is set to the level of the interrupt being acknowledged. the scm68000 fetches the vector number from the interrupting device by executing an interrupt acknowledge cycle, which displays the level number of the interrupt being acknowledged on the address bus. if external logic requests an automatic vector, the scm68000 internally generates a vector number corresponding to the interrupt level number. if external logic indi- cates a bus error, the interrupt is considered spurious, and the generated vector number ref- erences the spurious interrupt vector. the scm68000 then proceeds with the usual exception processing, saving the program counter and status register on the supervisor stack. the saved value of the program counter is the address of the instruction that would have been executed had the interrupt not been taken. the appropriate interrupt vector is fetched and loaded into the program counter, and normal instruction execution commences in the interrupt handling routine. figure 4-13. initialization of the scm68000 for simulation timing diagram clki haltib resetib test 47 47 47 47 47 47 t 2 clock periods > > > > > t 2 clock periods t 0 clock periods > > t 10 clock periods f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing 4-20 ec000 core processor user? manual motorola interrupt requests should be maintained on the interrupt control signals iplb2?plb0 until the interrupt acknowledge bus cycle is initiated to guarantee that the interrupt will be recog- nized. 4.3.2.1 level seven interrupts. level seven interrupts are handled differently than interrupt levels one through six. a level seven interrupt is a nonmaskable interrupt; therefore, a seven in the interrupt mask does not disable a level seven interrupt. level seven interrupts are edge triggered by a transition from a lower priority request to the level seven request, as opposed to interrupt levels one through six, which are level sensitive. therefore, if iplb2-iplb0 remain at level seven, the scm68000 will only recognize one lev- el seven interrupt since only one transition from a lower level request to a level seven re- quest occurred. for the processor to recognize a level seven interrupt followed by another level seven interrupt, one of the two following sequences must occur: 1. the interrupt request level on the interrupt control pins changes from a lower request level to level seven and remains at level seven until the interrupt acknowledge bus cy- cle begins. later, the interrupt request level returns to a lower interrupt request level and then back to level seven, causing a second transition on the interrupt control lines. 2. the interrupt request level on the interrupt control pins changes from a lower request level to level seven and remains at level seven. if the interrupt handling routine for the level seven interrupt lowers the interrupt mask level, a second level seven interrupt will be recognized even though no transition has occurred on the interrupt control pins. af- ter the level seven interrupt handling routine completes, the scm68000 will compare the interrupt mask level to the interrupt request level on iplb2-iplb0. since the inter- rupt mask level will be lower than the requested level, the interrupt mask will be set back to level seven. the level seven request on iplb2-iplb0 must be held until the second interrupt acknowledge bus cycle has begun to insure that the interrupt is rec- ognized. for more information on scm68000 interrupts, see the application note a discussion of interrupts for the mc68000 (an1012). 4.3.2.2 uninitialized interrupt. under normal conditions, an interrupting device pro- vides the scm68000 with an interrupt vector number and asserts data transfer acknowledge (dtackb), or asserts autovector (avecb), or bus error (berrb) during an interrupt acknowledge cycle by the scm68000. if the interrupting m68000 family peripheral has not been initialized, it will provide the uninitialized interrupt vector number ($0f). this response conforms to a uniform way to recover from a programming error. 4.3.2.3 spurious interrupt. during the interrupt acknowledge cycle, if no device responds by asserting dtackb or avecb, berrb should be asserted to terminate the vector acquisition. the scm68000 separates the processing of this error from bus error by forming a short format exception stack and fetching the spurious interrupt vector instead of the bus error vector. the scm68000 then proceeds with the usual exception processing. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing motorola ec000 core processor user? manual 4-21 4.3.3 instruction traps traps are exceptions caused by instructions. traps occur when the scm68000 recognizes an abnormal condition during instruction execution or when an instruction that normally causes exception processing is executed. exception processing for traps is straightforward. the status register is copied; the supervi- sor mode is entered; and tracing is turned off. the vector number is internally generated; for the trap instruction, part of the vector number comes from the instruction itself. the pro- gram counter and the copy of the status register are saved on the supervisor stack. the saved value of the program counter is the address of the instruction following the instruction that generated the trap. finally, instruction execution commences at the address in the exception vector. some instructions are used specifically to generate traps. the trap instruction always forces an exception and is useful for implementing system calls for user programs. the trapv and chk instructions force an exception if the user program detects a run-time error, which may be an arithmetic overflow or a subscript out of bounds. a signed divide (divs) or unsigned divide (divu) instruction forces an exception if a division operation is attempted with a divisor of zero. 4.3.4 illegal and unimplemented instructions illegal instruction is the term used to refer to any of the word bit patterns that do not match a legal scm68000 instruction. if such an instruction is fetched, an illegal instruction excep- tion occurs. motorola reserves the right to define instructions using the opcodes of any of the illegal instructions. three bit patterns always force an illegal instruction trap: $4afa, $4afb, and $4afc. two of the patterns, $4afa and $4afb, are reserved for motorola sys- tem products. the third pattern, $4afc, is reserved for customer use (as the take illegal instruction trap (illegal ) instruction). word patterns with bits 15?2 equaling 1010 or 1111 are distinguished as unimplemented instructions, and separate exception vectors are assigned to these patterns to permit effi- cient emulation. these vectors allow the operating system to emulate unimplemented instructions in software. exception processing for illegal instructions is similar to that of traps. after the instruction is fetched and decoding is attempted, the scm68000 determines that execution of an illegal instruction is being attempted and starts exception processing. the exception stack frame for group 2 (see table 4-3 for more information on exception groups) is then pushed on the supervisor stack, and the illegal instruction vector is fetched. 4.3.5 privilege violations to provide system security, various instructions are privileged. an attempt to execute one of the privileged instructions while in the user mode causes an exception. the privileged instructions can be found in chapter 6 of the m68000 family programmer? reference man- ual (m68000pm/ad). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing 4-22 ec000 core processor user? manual motorola exception processing for privilege violations is similar to that of illegal instructions. after the instruction is fetched and decoded and the scm68000 determines that a privilege violation is being attempted, the scm68000 starts exception processing. the status register is cop- ied; the supervisor mode is entered; and tracing is turned off. the vector number is gener- ated to reference the privilege violation vector, and the current program counter and the copy of the status register are saved on the supervisor stack. finally, instruction execution commences at the address in the privilege violation exception vector. 4.3.6 tracing to aid in program development, the m68000 family includes a facility to allow tracing fol- lowing each instruction. when tracing is enabled, an exception is forced after each instruc- tion is executed. thus, a debugging program can monitor the execution of the program under test. the trace function is controlled by the t-bit in the supervisor portion of the status register. if the t-bit is cleared (off), tracing is disabled and instruction execution proceeds normally. if the t-bit is set (on) at the beginning of the execution of an instruction, a trace exception is generated after the instruction is completed. if the instruction is not executed because an interrupt is taken or because the instruction is illegal or privileged, the trace exception does not occur. the trace exception also does not occur if the instruction is aborted by the reset, bus error, or address error exceptions. if the instruction is executed and an interrupt is pend- ing upon completion, the trace exception is processed before the interrupt exception. during the execution of the instruction, if an exception is forced by that instruction, the exception processing for the instruction exception occurs before that of the trace exception. as an extreme illustration of these rules, consider the arrival of an interrupt during the exe- cution of a trap instruction while tracing is enabled. first, the trap exception is processed, then the trace exception, and finally, the interrupt exception. instruction execution resumes in the interrupt handler routine. after the execution of the instruction is complete and before the start of the next instruction, exception processing for a trace begins. a copy is made of the status register. the transition to supervisor mode is made, and the t-bit of the status register is turned off, disabling further tracing. the vector number is generated to reference the trace exception vector, and the cur- rent program counter and the copy of the status register are saved on the supervisor stack. the saved value of the program counter is the address of the next instruction. instruction execution commences at the address contained in the trace exception vector. 4.3.7 bus error a bus error exception is requested by external logic. the current bus cycle is terminated. the current scm68000 activity, whether instruction or exception processing, is terminated, and the scm68000 immediately begins exception processing. exception processing for a bus error follows the usual sequence of steps. the status register is copied, the supervisor mode is entered, and tracing is turned off. the vector number is generated to refer to the bus error vector. since the scm68000 is fetching the instruction or an operand when the error occurs, the context of the scm68000 is more detailed. to save f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing motorola ec000 core processor user? manual 4-23 more of this context, additional information is saved on the supervisor stack. the program counter and the copy of the status register are saved. the value saved for the program counter is advanced 2?0 bytes beyond the address of the first word of the instruction that made the reference causing the bus error. if the bus error occurred during the fetch of the next instruction, the saved program counter has a value in the vicinity of the current instruc- tion, even if the current instruction is a branch, a jump, or a return instruction. in addition to the usual information, the scm68000 saves its internal copy of the first word of the instruc- tion being processed and the address being accessed by the aborted bus cycle. specific information about the access is also saved: type of access (read or write), scm68000 activ- ity (processing an instruction), and function code outputs when the bus error occurred. the scm68000 is processing an instruction if it is in the normal state or processing a group 2 exception; the scm68000 is not processing an instruction if it is processing a group 0 or a group 1 exception (see table 4-3 for more information on exception groups). figure 4-14 illustrates how this information is organized on the supervisor stack. if a bus error occurs during the last step of exception processing, while either reading the exception vector or fetching the instruction, the value of the program counter is the address of the exception vec- tor. although this information is not generally sufficient to fully recover from the bus error, it does allow software diagnosis. finally, the scm68000 commences instruction processing at the address in the vector. it is the responsibility of the error handler routine to clean up the stack and determine where to continue execution. if a bus error or address error occurs during the exception processing for a bus error, an address error, or a reset, the scm68000 halts and all processing ceases. this halt simplifies the detection of a catastrophic system failure, since the scm68000 removes itself from the system to protect memory contents from erroneous accesses. only an external reset oper- ation can restart a halted scm68000. 4.3.8 address error an address error exception occurs when the scm68000 attempts to access a word or long- word operand or an instruction at an odd address. an address error is similar to an internally generated bus error. the bus cycle is aborted, and the scm68000 ceases current process- figure 4-14. supervisor stack order for bus or address error exception low high lower address r/w access address instruction register status register 543210 15 14 13 12 11 10 9 8 7 6 function code i/n program counter low high r/w (read/write): write = 0, read = 1. i/n (instruction/not): instruction = 0, not = 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing 4-24 ec000 core processor user? manual motorola ing and begins exception processing. the exception processing sequence is the same as that of a bus error, including the information to be stacked, except the vector number refers to the address error vector. likewise, if an address error occurs during the exception pro- cessing for a bus error, address error, or reset, the scm68000 is halted. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola ec000 core processor user? manual 5-1 section 5 8-bit instruction execution times this section contains listings of the instruction execution times in terms of external clock (clki) periods for the scm68000 (ec000 core) 1 in 8-bit mode. in this data, it is assumed that both memory read and write cycles consist of four clock periods. a longer memory cycle causes the generation of wait states that must be added to the total instruction times. the number of bus read and write cycles for each instruction is also included with the timing data. this data is shown as n(r/w) where: n is the total number of clock periods r is the number of read cycles w is the number of write cycles for example, a timing number shown as 18(3/1) means that 18 clock periods are required to execute the instruction. of the 18 clock periods, 12 are used for the three read cycles (four periods per cycle). four additional clock periods are used for the single write cycle, for a total of 16 clock periods. the bus is idle for two clock periods during which the processor com- pletes the internal operations required for the instruction. note the total number of clock periods (n) includes instruction fetch and all applicable operand fetches and stores. 5.1 operand effective address calculation times table 5-1 lists the numbers of clock periods required to compute the effective addresses for instructions. the totals include fetching any extension words, computing the address, and fetching the memory operand. the total number of clock periods, the number of read cycles, and the number of write cycles (zero for all effective address calculations) are shown in the previously described format. 1. the scm68000 is the name of the verilog model for the ec000 core. the remainder of this section will refer to the part as only the scm68000. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
8-bit instruction execution times 5-2 ec000 core processor user? manual motorola 5.2 move instruction execution times table 5-2, table 5-3, and table 5-4 list the numbers of clock periods required for the move instructions. the totals include instruction fetch, operand reads, and operand writes. the total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previously described format. table 5-1. effective address calculation times addressing mode byte word long register dn an data register direct address register direct 0 (0/0) 0 (0/0) 0 (0/0) 0 (0/0) 0 (0/0) 0 (0/0) memory (an) (an)+ address register indirect address register indirect with postincrement 4 (1/0) 4 (1/0) 8 (2/0) 8 (2/0) 16 (4/0) 16 (4/0) ?an) (d 16 , an) address register indirect with predecrement address register indirect with displacement 6 (1/0) 12 (3/0) 10 (2/0) 16 (4/0) 18 (4/0) 24 (6/0) (d 8 , an, xn)* (xxx).w address register indirect with index absolute short 14 (3/0) 12 (3/0) 18 (4/0) 16 (4/0) 26 (6/0) 24 (6/0) (xxx).l (d 16 , pc) absolute long program counter indirect with displacement 20 (5/0) 12 (3/0) 24 (6/0) 16 (3/0) 32 (8/0) 24 (6/0) (d 8 , pc, xn)* # program counter indirect with index immediate 14 (3/0) 8 (2/0) 18 (4/0) 8 (2/0) 26 (6/0) 16 (4/0) *the size of the index register (xn) does not affect execution time. table 5-2. move byte instruction execution times source destination dn an (an) (an)+ ?an) (d 16 , an) (d 8 , an, xn)* (xxx).w (xxx).l dn (an) 8 (2/0) 12 (3/0) 8 (2/0) 12 (3/0) 12 (2/1) 16 (3/1) 12 (2/1) 16 (3/1) 12 (2/1) 16 (3/1) 20 (4/1) 24 (5/1) 22 (4/1) 26 (5/1) 20 (4/1) 24 (5/1) 28 (6/1) 32 (7/1) (an)+ ?an) (d 16 , an) 12 (3/0) 14 (3/0) 20 (5/0) 12 (3/0) 14 (3/0) 20 (5/0) 16 (3/1) 18 (3/1) 24 (5/1) 16 (3/1) 18 (3/1) 24 (5/1) 16 (3/1) 18 (3/1) 24 (5/1) 24 (5/1) 26 (5/1) 32 (7/1) 26 (5/1) 28 (5/1) 34 (7/1) 24 (5/1) 26 (5/1) 32 (7/1) 32 (7/1) 34 (7/1) 40 (9/1) (d 8 , an, xn)* (xxx).w (xxx).l 22 (5/0) 20 (5/0) 28 (7/0) 22 (5/0) 20 (5/0) 28 (7/0) 26 (5/1) 24 (5/1) 32 (7/1) 26 (5/1) 24 (5/1) 32 (7/1) 26 (5/1) 24 (5/1) 32 (7/1) 34 (7/1) 32 (7/1) 40 (9/1) 36 (7/1) 34 (7/1) 42 (9/1) 34 (7/1) 32 (7/1) 40 (9/1) 42 (9/1) 40 (9/1) 48 (11/1) (d 16 , pc) (d 8 , pc, xn)* # 20 (5/0) 22 (5/0) 16 (4/0) 20 (5/0) 22 (5/0) 16 (4/0) 24 (5/1) 26 (5/1) 20 (4/1) 24 (5/1) 26 (5/1) 20 (4/1) 24 (5/1) 26 (5/1) 20 (4/1) 32 (7/1) 34 (7/1) 28 (6/1) 34 (7/1) 36 (7/1) 30 (6/1) 32 (7/1) 34 (7/1) 28 (6/1) 40 (9/1) 42 (9/1) 36 (8/1) *the size of the index register (xn) does not affect execution time. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
8-bit instruction execution times motorola ec000 core processor user? manual 5-3 5.3 standard instruction execution times the numbers of clock periods listed in table 5-5 indicate the times required to perform the operations, store the results, and read the next instruction. the total number of clock peri- ods, the number of read cycles, and the number of write cycles are shown in the previously described format. the number of clock periods, the number of read cycles, and the number of write cycles, respectively, must be added to those of the effective address calculation where indicated by a plus sign (+). in table 5-5, the following notation applies: an address register operand dn data register operand ea an operand specified by an effective address m memory effective address operand table 5-3. move word instruction execution times source destination dn an (an) (an)+ ?an) (d 16 , an) (d 8 , an, xn)* (xxx).w (xxx).l dn an (an) 8 (2/0) 8 (2/0) 16 (4/0) 8 (2/0) 8 (2/0) 16 (4/0) 16 (2/2) 16 (2/2) 24 (4/2) 16 (2/2) 16 (2/2) 24 (4/2) 16 (2/2) 16 (2/2) 24 (4/2) 24 (4/2) 24 (4/2) 32 (6/2) 26 (4/2) 26 (4/2) 34 (6/2) 24 (4/2) 24 (4/2) 32 (6/2) 32 (6/2) 32 (6/2) 40 (8/2) (an)+ ?an) (d 16 , an) 16 (4/0) 18 (4/0) 24 (6/0) 16 (4/0) 18 (4/0) 24 (6/0) 24 (4/2) 26 (4/2) 32 (6/2) 24 (4/2) 26 (4/2) 32 (6/2) 24 (4/2) 26 (4/2) 32 (6/2) 32 (6/2) 34 (6/2) 40 (8/2) 34 (6/2) 32 (6/2) 42 (8/2) 32 (6/2) 34 (6/2) 40 (8/2) 40 (8/2) 42 (8/2) 48 (10/2) (d 8 , an, xn)* (xxx).w (xxx).l 26 (6/0) 24 (6/0) 32 (8/0) 26 (6/0) 24 (6/0) 32 (8/0) 34 (6/2) 32 (6/2) 40 (8/2) 34 (6/2) 32 (6/2) 40 (8/2) 34 (6/2) 32 (6/2) 40 (8/2) 42 (8/2) 40 (8/2) 48 (10/2) 44 (8/2) 42 (8/2) 50 (10/2) 42 (8/2) 40 (8/2) 48 (10/2) 50 (10/2) 48 (10/2) 56 (12/2) (d 16 , pc) (d 8 , pc, xn)* # 24 (6/0) 26 (6/0) 16 (4/0) 24 (6/0) 26 (6/0) 16 (4/0) 32 (6/2) 34 (6/2) 24 (4/2) 32 (6/2) 34 (6/2) 24 (4/2) 32 (6/2) 34 (6/2) 24 (4/2) 40 (8/2) 42 (8/2) 32 (6/2) 42 (8/2) 44 (8/2) 34 (6/2) 40 (8/2) 42 (8/2) 32 (6/2) 48 (10/2) 50 (10/2) 40 (8/2) *the size of the index register (xn) does not affect execution time. table 5-4. move long instruction execution times source destination dn an (an) (an)+ ?an) (d 16 , an) (d 8 , an, xn)* (xxx).w (xxx).l dn an (an) 8 (2/0) 8 (2/0) 24 (6/0) 8 (2/0) 8 (2/0) 24 (6/0) 24 (2/4) 24 (2/4) 40 (6/4) 24 (2/4) 24 (2/4) 40 (6/4) 24 (2/4) 24 (2/4) 40 (6/4) 32 (4/4) 32 (4/4) 48 (8/4) 34 (4/4) 34 (4/4) 50 (8/4) 32 (4/4) 32 (4/4) 48 (8/4) 40 (6/4) 40 (6/4) 56 (10/4) (an)+ ?an) (d 16 , an) 24 (6/0) 26 (6/0) 32 (8/0) 24 (6/0) 26 (6/0) 32 (8/0) 40 (6/4) 42 (6/4) 48 (8/4) 40 (6/4) 42 (6/4) 48 (8/4) 40 (6/4) 42 (6/4) 48 (8/4) 48 (8/4) 50 (8/4) 56 (10/4) 50 (8/4) 52 (8/4) 58 (10/4) 48 (8/4) 50 (8/4) 56 (10/4) 56 (10/4) 58 (10/4) 64 (12/4) (d 8 , an, xn)* (xxx).w (xxx).l 34 (8/0) 32 (8/0) 40 (10/0) 34 (8/0) 32 (8/0) 40 (10/0) 50 (8/4) 48 (8/4) 56 (10/4) 50 (8/4) 48 (8/4) 56 (10/4) 50 (8/4) 48 (8/4) 56 (10/4) 58 (10/4) 56 (10/4) 64 (12/4) 60 (10/4) 58 (10/4) 66 (12/4) 58 (10/4) 56 (10/4) 64 (12/4) 66 (12/4) 64 (12/4) 72 (14/4) (d 16 , pc) (d 8 , pc, xn)* # 32 (8/0) 34 (8/0) 24 (6/0) 32 (8/0) 34 (8/0) 24 (6/0) 48 (8/4) 50 (8/4) 40 (6/4) 48 (8/4) 50 (8/4) 40 (6/4) 48 (8/4) 50 (8/4) 40 (6/4) 56 (10/4) 58 (10/4) 48 (8/4) 58 (10/4) 60 (10/4) 50 (8/4) 56 (10/4) 58 (10/4) 48 (8/4) 64 (12/4) 66 (12/4) 56 (10/4) *the size of the index register (xn) does not affect execution time. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
8-bit instruction execution times 5-4 ec000 core processor user? manual motorola 5.4 immediate instruction execution times the numbers of clock periods listed in table 5-6 include the times to fetch immediate oper- ands, perform the operations, store the results, and read the next operation. the total num- ber of clock periods, the number of read cycles, and the number of write cycles are shown in the previously described format. the number of clock periods, the number of read cycles, and the number of write cycles, respectively, must be added to those of the effective address calculation where indicated by a plus sign (+). in table 5-6, the following notation applies: # immediate operand dn data register operand an address register operand m memory operand table 5-5. standard instruction execution times instruction size op, an op, dn op dn, add/adda byte word long 12 (2/0)+ 10 (2/0)+** 8 (2/0)+ 8 (2/0)+ 10 (2/0)+** 12 (2/1)+ 16 (2/2)+ 24 (2/4)+ and byte word long 8 (2/0)+ 8 (2/0)+ 10 (2/0)+** 12 (2/1)+ 16 (2/2)+ 24 (2/4)+ cmp/cmpa byte word long 10 (2/0)+ 10 (2/0)+ 8 (2/0)+ 8 (2/0)+ 10 (2/0)+ divs divu word word 162 (2/0)+* 144 (2/0)+* eor byte word long 8 (2/0)+*** 8(2/0)+*** 12 (2/0)+*** 12 (2/1)+ 16 (2/2)+ 24 (2/4)+ muls mulu word word 74 (2/0)+* 74 (2/0)+* or byte word long 8 (2/0)+ 8(2/0)+ 10 (2/0)+** 12 (2/1)+ 16 (2/2)+ 24 (2/4)+ sub byte word long 12 (2/0)+ 10 (2/0)+** 8 (2/0)+ 8(2/0)+ 10 (2/0)+** 12 (2/1)+ 16 (2/2)+ 24 (2/4)+ +add effective address calculation time. *indicates maximum base value added to word effective address time. **the base time of 10 clock periods is increased to 12 if the effective address mode is register direct or immediate (effective address time should also be added). ***only available effective address mode is data register direct. muls, mulu?he multiply algorithm requires 42+2n clocks where n is de?ed as: muls: n = tag the with a zero as the msb; n is the resultant number of 10 or 01 patterns in the 17-bit source; i.e., worst case happens when the source is $5555. mulu: n = the number of ones in the f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
8-bit instruction execution times motorola ec000 core processor user? manual 5-5 5.5 single operand instruction execution times table 5-7 lists the timing data for the single operand instructions. the total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previ- ously described format. the number of clock periods, the number of read cycles, and the number of write cycles, respectively, must be added to those of the effective address calcu- lation where indicated by a plus sign (+). table 5-6. immediate instruction execution times instruction size op #, dn op #, an op #, m addi byte word long 16 (4/0) 16 (4/0) 28 (6/0) 20 (4/1)+ 24 (4/2)+ 40 (6/4)+ addq byte word long 8 (2/0) 8 (2/0) 12 (2/0) 12 (2/0) 12 (2/0) 12 (2/1)+ 16 (2/2)+ 24 (2/4)+ andi byte word long 16 (4/0) 16 (4/0) 28 (6/0) 20 (4/1)+ 24 (4/2)+ 40 (6/4)+ cmpi byte word long 16 (4/0) 16 (4/0) 26 (6/0) 16 (4/0) 16 (4/0) 24 (6/0) eori byte word long 16 (4/0) 16 (4/0) 28 (6/0) 20 (4/1)+ 24 (4/2)+ 40 (6/4)+ moveq long 8 (2/0) ori byte word long 16 (4/0) 16 (4/0) 28 (6/0) 20 (4/1)+ 24 (4/2)+ 40 (6/4)+ subi byte word long 16 (4/0) 16 (4/0) 28 (6/0) 12 (2/1)+ 16 (2/2)+ 24 (2/4)+ subq byte word long 8 (2/0) 8 (2/0) 12 (2/0) 12 (2/0) 12 (2/0) 20 (4/1)+ 24 (4/2)+ 40 (6/4)+ + add effective address calculation time. table 5-7. single operand instruction execution times instruction size register memory clr byte word long 8 (2/0) 8 (2/0) 10 (2/0) 12 (2/1)+ 16 (2/2)+ 24 (2/4)+ nbcd byte 10 (2/0) 12 (2/1)+ neg byte word long 8 (2/0) 8 (2/0) 10 (2/0) 12 (2/1)+ 16 (2/2)+ 24 (2/4)+ negx byte word long 8 (2/0) 8 (2/0) 10 (2/0) 12 (2/1)+ 16 (2/2)+ 24 (2/4)+ not byte word long 8 (2/0) 8 (2/0) 10 (2/0) 12 (2/1)+ 16 (2/2)+ 24 (2/4)+ scc byte, false byte, true 8 (2/0) 10 (2/0) 12 (2/1)+ 12 (2/1)+ tas byte 8 (2/0) 14 (2/1)+ tst byte word long 8 (2/0) 8 (2/0) 8 (2/0) 8 (2/0)+ 8 (2/0)+ 8 (2/0)+ + add effective address calculation time. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
8-bit instruction execution times 5-6 ec000 core processor user? manual motorola 5.6 shift/rotate instruction execution times table 5-8 lists the timing data for the shift and rotate instructions. the total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previ- ously described format. the number of clock periods, the number of read cycles, and the number of write cycles, respectively, must be added to those of the effective address calcu- lation where indicated by a plus sign (+). 5.7 bit manipulation instruction execution timess table 5-9 lists the timing data for the bit manipulation instructions. the total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previ- ously described format. the number of clock periods, the number of read cycles, and the number of write cycles, respectively, must be added to those of the effective address calcu- lation where indicated by a plus sign (+). 5.8 conditional instruction execution times table 5-10 lists the timing data for the conditional instructions. the total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previ- ously described format. the number of clock periods, the number of read cycles, and the number of write cycles, respectively, must be added to those of the effective address calcu- lation where indicated by a plus sign (+). table 5-8. shift/rotate instruction execution times instruction size register memory asr, asl byte word long 10+2n (2/0) 10+2n (2/0) 12+n2 (2/0) 16 (2/2)+ lsr, lsl byte word long 10+2n (2/0) 10+2n (2/0) 12+n2 (2/0) 16 (2/2)+ ror, rol byte word long 10+2n (2/0) 10+2n (2/0) 12+n2 (2/0) 16 (2/2)+ roxr, roxl byte word long 10+2n (2/0) 10+2n (2/0) 12+n2 (2/0) 16 (2/2)+ + add effective address calculation time for word operands. n is the shift count. table 5-9. bit manipulation instruction execution times instruction size dynamic static register memory register memory bchg byte long 12 (2/0)* 12 (2/1)+ 20 (4/0)* 20 (4/1)+ bclr byte long 14 (2/0)* 12 (2/1)+ 22 (4/0)* 20 (4/1)+ bset byte long 12 (2/0)* 12 (2/1)+ 20 (4/0)* 20 (4/1)+ btst byte long 10 (2/0) 8 (2/0)+ 18 (4/0) 16 (4/0)+ + add effective address calculation time. * indicates maximum value; data addressing mode only. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
8-bit instruction execution times motorola ec000 core processor user? manual 5-7 5.9 jmp, jsr, lea, pea, and movem instruction execution times table 5-11 lists the timing data for the jump (jmp), jump to subroutine (jsr), load effective address (lea), push effective address (pea), and move multiple registers (movem) instructions. the total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previously described format. 5.10 multiprecision instruction execution times table 5-12 lists the timing data for multiprecision instructions. the numbers of clock periods include the times to fetch both operands, perform the operations, store the results, and read the next instructions. the total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previously described format. table 5-10. conditional instruction execution times instruction displacement trap or branch taken trap or branch not taken bcc byte word 18 (4/0) 18 (4/0) 12 (2/0) 20 (4/0) bra byte word 18 (4/0) 18 (4/0) bsr byte word 34 (4/4) 34 (4/4) dbcc cc true cc false 18 (4/0) 20 (4/0) 26 (6/0) chk 68 (8/6)+* 14 (2/0)+ trapv 66 (10/6) 8 (2/0) + add effective address calculation time for word operand. * indicates maximum base value. table 5-11. jmp, jsr, lea, pea, and movem instruction execution times instruction size (an) (an)+ ?an) (d 16 ,an) (d 8 ,an,xn)+ (xxx).w (xxx).l (d 16 pc) (d 8 , pc, xn)* jmp 16 (4/0) 18 (4/0) 22 (4/0) 18 (4/0) 24 (6/0) 18 (4/0) 22 (4/0) jsr 32 (4/4) 34 (4/4) 38 (4/4) 34 (4/4) 40 (6/4) 34 (4/4) 32 (4/4) lea 8 (2/0) 16 (4/0) 20 (4/0) 16 (4/0) 24 (6/0) 16 (4/0) 20 (4/0) pea 24 (2/4) 32 (4/4) 36 (4/4) 32 (4/4) 40 (6/4) 32 (4/4) 36 (4/4) movem m r word long 24+8n (6+2n/0) 24+8n (6+2n/0) 32+8n (8+2n/0) 34+8n (8+2n/0) 32+8n (10+n/0) 40+8n (10+2n/0) 32+8n (8+2n/0) 34+8n (8+2n/0) 24+16n (6+4n/0) 24+16n (6+4n/0) 32+16n (8+4n/0) 34+16n (8+4n/0) 32+16n (8+4n/0) 40+16n (8+4n/0) 32+16n (8+4n/0) 34+16n (8+4n/0) movem r m word long 16+8n (4/2n) 16+8n (4/2n) 24+8n (6/2n) 26+8n (6/2n) 24+8n (6/2n) 32+8n (8/2n) 16+16n (4/4n) 16+16n (4/4n) 24+16n (6/4n) 26+16n 24+16n (8/4n) 32+16n (6/4n) *the size of the index register (xn) does not affect the instruction's execution time. n is the number of registers to move. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
8-bit instruction execution times 5-8 ec000 core processor user? manual motorola the following notation applies in table 5-12: dn data register operand m memory operand 5.11 miscellaneaous instruction execution times table 5-13 and table 5-14 list the timing data for miscellaneous instructions. the total num- ber of clock periods, the number of read cycles, and the number of write cycles are shown in the previously described format. the number of clock periods, the number of read cycles, and the number of write cycles, respectively, must be added to those of the effective address calculation where indicated by a plus sign (+). table 5-12. multiprecision instruction execution times instruction size op dn, dn op m, m addx byte word long 8 (2/0) 8 (2/0) 12 (2/0) 22 (4/1) 50 (6/2) 58 (10/4) cmpm byte word long 16 (4/0) 24 (6/0) 40 (10/0) subx byte word long 8 (2/0) 8 (2/0) 12 (2/0) 22 (4/1) 50 (6/2) 58 (10/4) abcd byte 10 (2/0) 20 (4/1) sbcd byte 10 (2/0) 20 (4/1) table 5-13. miscellaneous instruction execution times instruction register memory andi to ccr 32 (6/0) andi to sr 32 (6/0) eori to ccr 32 (6/0) eori to sr 32 (6/0) exg 10 (2/0) ext 8 (2/0) link 32 (4/4) move to ccr 18 (4/0) 18 (4/0)+ move to sr 18 (4/0) 18 (4/0)+ move from sr 10 (2/0) 16 (2/2)+ move to usp 8 (2/0) move from usp 8 (2/0) nop 8 (2/0) ori to ccr 32 (6/0) ori to sr 32 (6/0) reset 136 (2/0) rte 40 (10/0) rtr 40 (10/0) rts 32 (8/0) stop 4 (0/0) swap 8 (2/0) unlk 24 (6/0) + add effective address calculation time for word operand. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
8-bit instruction execution times motorola ec000 core processor user? manual 5-9 5.12 exception processing execution times table 5-15 lists the timing data for exception processing. the numbers of clock periods include the times for all stacking, the vector fetch, and the fetch of the first instruction of the handler routine. the total number of clock periods, the number of read cycles, and the num- ber of write cycles are shown in the previously described format. the number of clock peri- ods, the number of read cycles, and the number of write cycles, respectively, must be added to those of the effective address calculation where indicated by a plus sign (+). table 5-14. move peripheral instruction execution times instruction size register memory memory register movep word long 24 (4/2) 32 (4/4) 24 (6/0) 32 (8/0) + add effective address calculation time. table 5-15. exception processing execution times exception periods address error 94 (8/14) bus error 94 (8/14) chk instruction 68 (8/6)+ divide-by-zero 66 (8/6)+ interrupt 72 (9/6)* illegal instruction 62 (8/6) privilege violation 62 (8/6) reset** 64 (12/0) trace 62 (8/6) trap instruction 62 (8/6) trapv instruction 66 (10/6) +add effective address calculation time. *the interrupt acknowledge cycle is assumed to take four clock periods. **indicates the time from when reset and halt are ?st sampled as negated to when instruction execution starts. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
8-bit instruction execution times 5-10 ec000 core processor user? manual motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola ec000 core processor user? manual 6-1 section 6 16-bit instruction execution times this section contains listings of the instruction execution times in terms of external clock (clki) periods for the scm68000 (ec000 core) 1 in 16-bit mode. in this data, it is assumed that both memory read and write cycles consist of four clock periods. a longer memory cycle causes the generation of wait states that must be added to the total instruction times. the number of bus read and write cycles for each instruction is also included with the timing data. this data is shown as n(r/w) where: n is the total number of clock periods r is the number of read cycles w is the number of write cycles for example, a timing number shown as 18(3/1) means that the total number of clock peri- ods is 18. of the 18 clock periods, 12 are used for the three read cycles (four periods per cycle). four additional clock periods are used for the single write cycle, for a total of 16 clock periods. the bus is idle for two clock periods during which the processor completes the inter- nal operations required for the instruction. note the total number of clock periods (n) includes instruction fetch and all applicable operand fetches and stores. 6.1 operand effective address calculation times table 6-1 lists the numbers of clock periods required to compute the effective addresses for instructions. the totals include fetching any extension words, computing the address, and fetching the memory operand. the total number of clock periods, the number of read cycles, and the number of write cycles (zero for all effective address calculations) are shown in the previously described format. 1. the scm68000 is the name of the verilog model for the ec000 core. the remainder of this section will refer to the part as only the scm68000. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16-bit instruction execution times 6-2 ec000 core processor user? manual motorola 6.2 move instruction execution times table 6-2 and table 6-3 list the numbers of clock periods required for the move instructions. the totals include instruction fetch, operand reads, and operand writes. the total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previously described format. table 6-1. effective address calculation times addressing mode byte, word long register dn an data register direct address register direct 0 (0/0) 0 (0/0) 0 (0/0) 0 (0/0) memory (an) (an)+ address register indirect address register indirect with postincrement 4 (1/0) 4 (1/0) 8 (2/0) 8 (2/0) ?an) (d 16 , an) address register indirect with predecrement address register indirect with displacement 6 (1/0) 8 (2/0) 10 (2/0) 12 (3/0) (d 8 , an, xn)* (xxx).w address register indirect with index absolute short 10 (2/0) 8 (2/0) 14 (3/0) 12 (3/0) (xxx).l (d 8 , pc) absolute long program counter indirect with displacement 12 (3/0) 8 (2/0) 16 (4/0) 12 (3/0) (d 16 , pc, xn)* # program counter indirect with index immediate 10 (2/0) 4 (1/0) 14 (3/0) 8 (2/0) *the size of the index register (xn) does not affect execution time. table 6-2. move byte and word instruction execution times source destination dn an (an) (an)+ ?an) (d 16 , an) (d 8 , an, xn)* (xxx).w (xxx).l dn an** (an) 4 (1/0) 4 (1/0) 8 (2/0) 4 (1/0) 4 (1/0) 8 (2/0) 8 (1/1) 8 (1/1) 12 (2/1) 8 (1/1) 8 (1/1) 12 (2/1) 8 (1/1) 8 (1/1) 12 (2/1) 12 (2/1) 12 (2/1) 16 (3/1) 14 (2/1) 14 (2/1) 18 (3/1) 12 (2/1) 12 (2/1) 16 (3/1) 16 (3/1) 16 (3/1) 20 (4/1) (an)+ ?an) (d 16 , an) 8 (2/0) 10 (2/0) 12 (3/0) 8 (2/0) 10 (2/0) 12 (3/0) 12 (2/1) 14 (2/1) 16 (3/1) 12 (2/1) 14 (2/1) 16 (3/1) 12 (2/1) 14 (2/1) 16 (3/1) 16 (3/1) 18 (3/1) 20 (4/1) 18 (3/1) 20 (3/1) 22 (4/1) 16 (3/1) 18 (3/1) 20 (4/1) 20 (4/1) 22 (4/1) 24 (5/1) (d 8 , an, xn)* (xxx).w (xxx).l 14 (3/0) 12 (3/0) 16 (4/0) 14 (3/0) 12 (3/0) 16 (4/0) 18 (3/1) 16 (3/1) 20 (4/1) 18 (3/1) 16 (3/1) 20 (4/1) 18 (3/1) 16 (3/1) 20 (4/1) 22 (4/1) 20 (4/1) 24 (5/1) 24 (4/1) 22 (4/1) 26 (5/1) 22 (4/1) 20 (4/1) 24 (5/1) 26 (5/1) 24 (5/1) 28 (6/1) (d 16 , pc) (d 8 , pc, xn)* # 12 (3/0) 14 (3/0) 8 (2/0) 12 (3/0) 14 (3/0) 8 (2/0) 16 (3/1) 18 (3/1) 12 (2/1) 16 (3/1) 18 (3/1) 12 (2/1) 16 (3/1) 18 (3/1) 12 (2/1) 20 (4/1) 22 (4/1) 16 (3/1) 22 (4/1) 24 (4/1) 18 (3/1) 20 (4/1) 22 (4/1) 16 (3/1) 24 (5/1) 26 (5/1) 20 (4/1) *the size of the index register (xn) does not affect execution time. **only word operands; byte operands not allowed. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16-bit instruction execution times motorola ec000 core processor user? manual 6-3 6.3 standard instruction execution times the numbers of clock periods listed in table 6-4 indicate the times required to perform the operations, store the results, and read the next instruction. the total number of clock peri- ods, the number of read cycles, and the number of write cycles are shown in the previously described format. the number of clock periods, the number of read cycles, and the number of write cycles, respectively, must be added to those of the effective address calculation where indicated by a plus sign (+). in table 6-4, the following notation applies: an address register operand dn data register operand ea an operand specified by an effective address m memory effective address operand table 6-3. move long instruction execution times source destination dn an (an) (an)+ ?an) (d 16 , an) (d 8 , an, xn)* (xxx).w (xxx).l dn an (an) 4 (1/0) 4 (1/0) 12 (3/0) 4 (1/0) 4 (1/0) 12 (3/0) 12 (1/2) 12 (1/2) 20 (3/2) 12 (1/2) 12 (1/2) 20 (3/2) 12 (1/2) 12 (1/2) 20 (3/2) 16 (2/2) 16 (2/2) 24 (4/2) 18 (2/2) 18 (2/2) 26 (4/2) 16 (2/2) 16 (2/2) 24 (4/2) 20 (3/2) 20 (3/2) 28 (5/2) (an)+ ?an) (d 16 , an) 12 (3/0) 14 (3/0) 16 (4/0) 12 (3/0) 14 (3/0) 16 (4/0) 20 (3/2) 22 (3/2) 24 (4/2) 20 (3/2) 22 (3/2) 24 (4/2) 20 (3/2) 22 (3/2) 24 (4/2) 24 (4/2) 26 (4/2) 28 (5/2) 26 (4/2) 28 (4/2) 30 (5/2) 24 (4/2) 26 (4/2) 28 (5/2) 28 (5/2) 30 (5/2) 32 (6/2) (d 8 , an, xn)* (xxx).w (xxx).l 18 (4/0) 16 (4/0) 20 (5/0) 18 (4/0) 16 (4/0) 20 (5/0) 26 (4/2) 24 (4/2) 28 (5/2) 26 (4/2) 24 (4/2) 28 (5/2) 26 (4/2) 24 (4/2) 28 (5/2) 30 (5/2) 28 (5/2) 32 (6/2) 32 (5/2) 30 (5/2) 34 (6/2) 30 (5/2) 28 (5/2) 32 (6/2) 34 (6/2) 32 (6/2) 36 (7/2) (d, pc) (d, pc, xn)* # 16 (4/0) 18 (4/0) 12 (3/0) 16 (4/0) 18 (4/0) 12 (3/0) 24 (4/2) 26 (4/2) 20 (3/2) 24 (4/2) 26 (4/2) 20 (3/2) 24 (4/2) 26 (4/2) 20 (3/2) 28 (5/2) 30 (5/2) 24 (4/2) 30 (5/2) 32 (5/2) 26 (4/2) 28 (5/2) 30 (5/2) 24 (4/2) 32 (5/2) 34 (6/2) 28 (5/2) *the size of the index register (xn) does not affect execution time. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16-bit instruction execution times 6-4 ec000 core processor user? manual motorola 6.4 immediate instruction execution times the numbers of clock periods listed in table 6-5 include the times to fetch immediate oper- ands, perform the operations, store the results, and read the next operation. the total num- ber of clock periods, the number of read cycles, and the number of write cycles are shown in the previously described format. the number of clock periods, the number of read cycles, and the number of write cycles, respectively, must be added to those of the effective address calculation where indicated by a plus sign (+). in table 6-5, the following notation applies: # immediate operand dn data register operand an address register operand m memory operand table 6-4. standard instruction execution times instruction size op, an? op, dn op dn, add/adda byte, word long 8 (1/0)+ 6 (1/0)+** 4 (1/0)+ 6 (1/0)+** 8 (1/1)+ 12 (1/2)+ and byte, word long 4 (1/0)+ 6 (1/0)+** 8 (1/1)+ 12 (1/2)+ cmp/cmpa byte, word long 6 (1/0)+ 6 (1/0)+ 4 (1/0)+ 6 (1/0)+ divs divu word word 158 (1/0)+* 140 (1/0)+* eor byte, word long 4 (1/0)*** 8 (1/0)*** 8 (1/1)+ 12 (1/2)+ muls mulu word word 70 (1/0)+* 70 (1/0)+* or byte, word long 4 (1/0)+ 6 (1/0)+** 8 (1/1)+ 12 (1/2)+ sub byte, word long 8 (1/0)+ 6 (1/0)+** 4 (1/0)+ 6 (1/0)+** 8 (1/1)+ 12 (1/2)+ +add effective address calculation time. ?word or long only. *indicates maximum basic value added to word effective address time. **the base time of six clock periods is increased to eight if the effective address mode is register direct or immediate (effective address time should also be added). ***only available effective address mode is data register direct. muls, mulu?he multiply algorithm requires 38+2n clocks where n is de?ed as: mulu: n = the number of ones in the muls: n=concatenate the with a zero as the lsb; n is the resultant number of 10 or 01 patterns in the 17-bit source; i.e., worst case happens when the source is $5555. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16-bit instruction execution times motorola ec000 core processor user? manual 6-5 6.5 single operand instruction execution times table 6-6 lists the timing data for the single operand instructions. the total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previ- ously described format. the number of clock periods, the number of read cycles, and the number of write cycles, respectively, must be added to those of the effective address calcu- lation where indicated by a plus sign (+). table 6-5. immediate instruction execution times instruction size op #, dn op #, an op #, m addi byte, word long 8 (2/0) 16 (3/0) 12 (2/1)+ 20 (3/2)+ addq byte, word long 4 (1/0) 8 (1/0) 4 (1/0)* 8 (1/0) 8 (1/1)+ 12 (1/2)+ andi byte, word long 8 (2/0) 14 (3/0) 12 (2/1)+ 20 (3/2)+ cmpi byte, word long 8 (2/0) 14 (3/0) 8 (2/0)+ 12 (3/0)+ eori byte, word long 8 (2/0) 16 (3/0) 12 (2/1)+ 20 (3/2)+ moveq long 4 (1/0) ori byte, word long 8 (2/0) 16 (3/0) 12 (2/1)+ 20 (3/2)+ subi byte, word long 8 (2/0) 16 (3/0) 12 (2/1)+ 20 (3/2)+ subq byte, word long 4 (1/0) 8 (1/0) 8 (1/0)* 8 (1/0) 8 (1/1)+ 12 (1/2)+ table 6-6. single operand instruction execution times instruction size register memory clr byte, word long 4 (1/0) 6 (1/0) 8 (1/1)+ 12 (1/2)+ nbcd byte 6 (1/0) 8 (1/1)+ neg byte, word long 4 (1/0) 6 (1/0) 8 (1/1)+ 12 (1/2)+ negx byte, word long 4 (1/0) 6 (1/0) 8 (1/1)+ 12 (1/2)+ not byte, word long 4 (1/0) 6 (1/0) 8 (1/1)+ 12 (1/2)+ scc byte, false byte, true 4 (1/0) 6 (1/0) 8 (1/1)+ 8 (1/1)+ tas byte 4 (1/0) 14 (2/1)+ tst byte, word long 4 (1/0) 4 (1/0) 4 (1/0)+ 4 (1/0)+ + add effective address calculation time. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16-bit instruction execution times 6-6 ec000 core processor user? manual motorola 6.6 shift/rotate instruction execution times table 6-7 lists the timing data for the shift and rotate instructions. the total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previ- ously described format. the number of clock periods, the number of read cycles, and the number of write cycles, respectively, must be added to those of the effective address calcu- lation where indicated by a plus sign (+). 6.7 bit manipulation instruction execution times table 6-8 lists the timing data for the bit manipulation instructions. the total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previ- ously described format. the number of clock periods, the number of read cycles, and the number of write cycles, respectively, must be added to those of the effective address calcu- lation where indicated by a plus sign (+). table 6-7. shift/rotate instruction execution times instruction size register memory asr, asl byte, word long 6+2n (1/0) 8+2n (1/0) 8 (1/1)+ lsr, lsl byte, word long 6+2n (1/0) 8+2n (1/0) 8 (1/1)+ ror, rol byte, word long 6+2n (1/0) 8+2n (1/0) 8 (1/1)+ roxr, roxl byte, word long 6+2n (1/0) 8+2n (1/0) 8 (1/1)+ + add effective address calculation time for word operands. n is the shift count. table 6-8. bit manipulation instruction execution times instruction size dynamic static register memory register memory bchg byte long 8 (1/0)* 8 (1/1)+ 12 (2/0)* 12 (2/1)+ bclr byte long 10 (1/0)* 8 (1/1)+ 14 (2/0)* 12 (2/1)+ bset byte long 8 (1/0)* 8 (1/1)+ 12 (2/0)* 12 (2/1)+ btst byte long 6 (1/0) 4 (1/0)+ 10 (2/0) 8 (2/0)+ + add effective address calculation time. * indicates maximum value?ata addressing mode only. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16-bit instruction execution times motorola ec000 core processor user? manual 6-7 6.8 conditional instruction execution times table 6-9 lists the timing data for the conditional instructions. the total number of clock peri- ods, the number of read cycles, and the number of write cycles are shown in the previously described format. 6.9 jmp, jsr, lea, pea, and movem instruction execution times table 6-10 lists the timing data for the jump (jmp), jump to subroutine (jsr), load effective address (lea), push effective address (pea), and move multiple registers (movem) instructions. the total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previously described format. 6.10 multiprecision instruction execution times table 6-11 lists the timing data for multiprecision instructions. the number of clock periods includes the time to fetch both operands, perform the operations, store the results, and read the next instructions. the total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previously described format. table 6-9. conditional instruction execution times instruction displacement branch taken branch not taken bcc byte word 10 (2/0) 10 (2/0) 8 (1/0) 12 (2/0) bra byte word 10 (2/0) 10 (2/0) bsr byte word 18 (2/2) 18 (2/2) chk (no trap) 10 (1/0)+ dbcc cc true cc false 10 (2/0) 12 (2/0) 14 (3/0) trapv 4 (1/0) table 6-10. jmp, jsr, lea, pea, and movem instruction execution times instruction size (an) (an)+ ?an) (d 16 ,an) (d 8 ,an,xn)+ (xxx).w (xxx).l (d 16 pc) (d 8 , pc, xn)* jmp 8 (2/0) 10 (2/0) 14 (3/0) 10 (2/0) 12 (3/0) 10 (2/0) 14 (3/0) jsr 16 (2/2) 18 (2/2) 22 (2/2) 18 (2/2) 20 (3/2) 18 (2/2) 22 (2/2) lea 4 (1/0) 8 (2/0) 12 (2/0) 8 (2/0) 12 (3/0) 8 (2/0) 12 (2/0) pea 12 (1/2) 16 (2/2) 20 (2/2) 16 (2/2) 20 (3/2) 16 (2/2) 20 (2/2) movem m r word long 12+4n (3+n/0) 12+4n (3+n/0) 16+4n (4+n/0) 18+4n (4+n/0) 16+4n (4+n/0) 20+4n (5+n/0) 16+4n (4n/0) 18+4n (4+n/0) 12+8n (3+2n/ 0) 12+8n (3+n/0) 16+8n (4+2n/0) 18+8n (4+2n/0) 16+8n (4+2n/0) 20+8n (5+2n/0) 16+8n (4+2n/0) 18+8n (4+2n/0) movem r m word long 8+4n (2/n) 8+4n (2/n) 12+4n (3/n) 14+4n (3/n) 12+4n (3/n) 16+4n (4/n) 8+8n (2/2n) 8+8n (2/2n) 12+8n (3/2n) 14+8n (3/2n) 12+8n (3/2n) 16+8n (4/2n) n is the number of registers to move. *the size of the index register (xn) does not affect the instruction's execution time. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16-bit instruction execution times 6-8 ec000 core processor user? manual motorola the following notation applies in table 6-11: dn data register operand m memory operand 6.11 miscellaneous instruction execution times table 6-12 and table 6-13 list the timing data for miscellaneous instructions. the total num- ber of clock periods, the number of read cycles, and the number of write cycles are shown in the previously described format. the number of clock periods, the number of read cycles, and the number of write cycles, respectively, must be added to those of the effective address calculation where indicated by a plus sign (+). table 6-11. multiprecision instruction execution times instruction size op dn, dn op m, m addx byte, word long 4 (1/0) 8 (1/0) 18 (3/1) 30 (5/2) cmpm byte, word long 12 (3/0) 20 (5/0) subx byte, word long 4 (1/0) 8 (1/0) 18 (3/1) 30 (5/2) abcd byte 6 (1/0) 18 (3/1) sbcd byte 6 (1/0) 18 (3/1) table 6-12. miscellaneous instruction execution times instruction size register memory andi to ccr byte 20 (3/0) andi to sr word 20 (3/0) eori to ccr byte 20 (3/0) eori to sr word 20 (3/0) ori to ccr byte 20 (3/0) ori to sr word 20 (3/0) move from sr word 6 (1/0) 8 (1/1)+ move to ccr word 12 (1/0) 12 (1/0)+ move to sr word 12 (2/0) 12 (2/0)+ exg long 6 (1/0) ext word, long 4 (1/0) link word 16 (2/2) move from usp long 4 (1/0) move to usp long 4 (1/0) nop 4 (1/0) reset 132 (1/0) rte 20 (5/0) rtr 20 (2/0) rts 16 (4/0) stop 4 (0/0) swap 4 (1/0) unlk 12 (3/0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16-bit instruction execution times motorola ec000 core processor user? manual 6-9 6.12 exception processing execution times table 6-14 lists the timing data for exception processing. the numbers of clock periods include the times for all stacking, the vector fetch, and the fetch of the first instruction of the handler routine. the total number of clock periods, the number of read cycles, and the num- ber of write cycles are shown in the previously described format. the number of clock peri- ods, the number of read cycles, and the number of write cycles, respectively, must be added to those of the effective address calculation where indicated by a plus sign (+). + add effective address calculation time. table 6-13. move peripheral instruction execution times instruction size register memory memory register movep word long 16 (2/2) 24 (2/4) 16 (4/0) 24 (6/0) table 6-14. exception processing execution times exception periods address error 50 (4/7) bus error 50 (4/7) chk instruction 40 (4/3)+ divide-by-zero 38 (4/3)+ illegal instruction 34 (4/3) interrupt 44 (5/3)* privilege violation 34 (4/3) reset** 40 (6/0) trace 34 (4/3) trap instruction 34 (4/3) trapv instruction 34 (5/3) +add effective address calculation time. *the interrupt acknowledge cycle is assumed to take four clock periods. **indicates the time from when reset and halt are ?st sampled as negated to when instruction execution starts. table 6-12. miscellaneous instruction execution times f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16-bit instruction execution times 6-10 ec000 core processor user? manual motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola ec000 core processor user? manual 7-1 section 7 electrical characteristics this section provides information on the maximum ratings for the scm68000 (ec000 core) 1 . 7.1 maximum ratings 7.2 cmos considerations because the basic cmos cell is composed of two complementary transistors, a virtual semi- conductor controlled rectifier (scr) may be formed when an input exceeds the supply volt- age. the scr that is formed by this high input causes the device to become latched in a mode that may result in excessive current drain and eventual destruction of the device. although the scm68000 is implemented with input protection diodes, care should be exer- cised to ensure that the maximum input voltage specification is not exceeded. some sys- tems may require that the cmos circuitry be isolated from voltage transients; other may require additional circuitry. 7.3 power consumption 7.4 ac electrical specification definitions the ac specifications presented consist of output delays, input setup and hold times, and signal skew times. all signals are specified relative to an appropriate edge of the clock and possibly to one or more other signals. 1. the scm68000 is the name of the verilog model for the ec000 core. the remainder of this section will refer to the part as only the scm68000. rating symbol value unit supply voltage v cc ?.3 to 7.0 v input voltage v in ?.3 to 7.0 v maximum operating temperature range t a t l to t h ?0 to100 c storage temperature t stg ?5 to 150 c characteristic 3.3 v 5 v unit typical max typical max operating current @16 mhz 15 30 25 50 ma standby current tbd tbd tbd tbd ma f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical characteristics 7-2 ec000 core processor user? manual motorola 7.5 ac electrical specifications?lock timing (see figure 7-1) 7.6 ac electrical specifications?ead and write cycles (frequency = 0 to 20 mhz; gnd = 0 v; t a = t l to t h ; see figure 7-2 and figure 7-3) num characteristic 3.3 v 5.0 v unit min max min max frequency of operation 20.0 20.0 mhz 1 cycle time 50 50 ns 2,3 clock pulse width 25 25 ns 4,5 clock rise and fall times ??ns figure 7-1. clock input timing diagram num characteristic 3.3 v 5.0 v unit min max min max 6 clock high to address valid 20 18 ns 6a clock high to fc valid 0 20 0 18 ns 7 clock high to address, data bus high impedance (maximum) (write) ?5?0ns 8 clock high to address, fc invalid (minimum) 0?ns 9 clock high to asb, dsb asserted 1 20 1 18 ns 11 1 address valid to asb, dsb asserted (read)/ asb asserted (write) 40?0ns 11a 1 fc valid to asb, dsb asserted (read)/asb asserted (write) 40 40 ns 12 clock low to asb, dsb negated 1 20 1 18 ns 13 1 asb, dsb negated to address, fc invalid 10 10 ns 14 1,5 asb and dsb width asserted (read)/asb width asserted (write) 100 100 ns 14a 6 dsb width asserted (write) 50 50 ns 15 1 asb, dsb width negated (read)/asb width negated (write) 50 50 ns 17 1,7 asb, dsb negated to rwb invalid 5?ns 18 clock high to rwb high (read) 0 20 0 18 ns 20 clock high to rwb low (write) 0 20 0 18 ns 20a asb asserted to rwb low (write) 10 10 ns 21 1 address valid to rwb low (write) 0?ns 21a 1 fc valid to rwb low (write) 25 25 ns 22 1 rwb low to dsb asserted (write) 10 10 ns 23 clock low to data-out valid (write) 20 18 ns 0.2 v dd 0.8 v dd timing measurements are referenced to and from a low voltage of 0.2 v dd and a high voltage of 0.8 v dd , unless otherwise noted. the voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.2 v dd and 0.8 v dd . 4 5 2 1 3 note: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical characteristics motorola ec000 core processor user? manual 7-3 25 1 asb, dsb negated to data-out invalid (write) 10 10 ns 26 1 data-out valid to dsb asserted (write) 10 10 ns 27 4 data-in valid to clock low (setup time on read) 5?ns 28 1 asb, dsb negated to dtackb negated (asynchronous hold) 0 95 0 95 ns 28a 1 clock high to dtackb negated 95 95 ns 29 asb, dsb negated to data-in invalid (hold time on read) 0?ns 29a asb, dsb negated to data-in high impedance (read) 75 75 ns 30 asb, dsb negated to berrb negated 0?ns 31 1,4 dtackb asserted to data-in valid (setup time on read) 42 42 ns 32 haltib and resetib input transition time 0 100 0 100 ns 47 4 asynchronous input setup time 5?ns 48 1,2 berrb asserted to dtackb asserted 10 10 ns 53 data-out hold from clock high (write) 0?ns 55 rwb asserted to data bus impedance change (write) 0?ns 56 3 haltib, resetib pulse width 10 10 clks notes: 1.actual value depends on clock period. 2.if #47 is satis?d for both dtackb and berrb, #48 may be ignored. in the absence of dtackb, berrb is an asynchronous input using the asynchronous input setup time (#47). 3.for power-up, the mc68000 must be held in the reset state for 132 clock cycles to allow stablization of on-chip circuitry. after the system is powered up, #56 refers to the minimum pulse width required to reset the processor. 4.if the asynchronous input setup time (#47) requirement is satis?d for dtackb, the dtackb asserted to data setup time (#31) requirement can be ignored. the data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle. 5.asb and dsb will be asserted from the rising edge of state 2 (s2) until the falling edge of state 7 (s7). 6.during a write, dsb will be asserted in state 4 (s4) and negated in s7. 7.with consecutive bus cycles, asb and dsb are negated from the falling edge of s7 to the rising edge of s2. num characteristic 3.3 v 5.0 v unit min max min max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical characteristics 7-4 ec000 core processor user? manual motorola figure 7-2. read cycle timing diagram 6a 8 6 13 14 12 17 18 47 28 29 27 48 47 30 47 32 56 47 32 s0 s1 s2 s3 s4 s5 s6 clki fc2?c0 a31?0 asb dsb/ldsb/udsb rwb dtackb data in berrb/brb (note 2) haltib/resetib 47 asynchronous inputs (note 1) s7 31 11 11a notes: 1. setup time for the asynchronous inputs iplb2?plb0 (spec #47) guarantees their recognition at the next falling edge of the clock. 2. brb need fall at this time only to ensure being recognized at the end of the bus cycle. 3. timing measurements are referenced to and from a low voltage of 0.2 v dd and a high voltage of 0.8 v dd , unless otherwise noted. the voltage swing through this range should start outside and pass through the range such that the rise or fall is linear between 0.2 v dd and 0.8 v dd . 9 28a 15 29a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical characteristics motorola ec000 core processor user? manual 7-5 figure 7-3. write cycle timing diagram 6a 8 6 15 13 9 14 12 17 18 47 28 25 26 48 47 30 47 32 56 47 32 s0 s1 s2 s3 s4 s5 s6 clk i fc2?c0 a31?0 asb dsb/ldsb/udsb rwb dtackb data out berrb/brb (note 2) haltib/resetib 47 asynchronous inputs (note 1) s7 notes: 1. timing measurements are referenced to and from a low voltage of 0.2 v dd and a high voltage of 0.8 v dd , unless otherwise noted. the voltage swing through this range should start outside and pass through the range such that the rise or fall is linear between 0.2 v dd and 0.8 v dd . 2. because of loading variations, rwb may be valid after asb even though both are initiated by the rising edge of s2 (specification #20a). 23 21a 7 11 11a 9 14a 28a 53 55 21 22 20a 20 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical characteristics 7-6 ec000 core processor user? manual motorola 7.7 ac electrical specifications?cm68000 to external peripherals (frequency = 0 to 20 mhz; gnd = 0 vdc; t a = t l to t h ; refer to figure 7-4) num characteristic 3.3 v 5.0 v unit min max min max 12 clock low to asb, dsb negated 1 20 1 18 ns 18 clock high to rwb high (read) 0 20 0 18 ns 20 clock high to rwb low (write) 0 20 0 20 ns 23 clock low to data-out valid (write) 20 18 ns 27 data-in valid to clock low (setup time on read) 5?ns 29 asb, dsb negated to data-in invalid (hold time on read) 0?ns 41 clock low to testclk transition 20 18 ns 42 testclk output rise and fall time 12 12 ns 44 asb, dsb negated to avecb negated 0 42 0 42 ns 45 testclk low to control, address bus invalid (address hold time) 10?0ns 47 asynchronous input setup time 5?ns 49 1 asb, dsb negated to testclk low ?0 30 ?0 30 ns 50 testclk width high 190 190 ns 51 testclk width low 290 290 ns 54 testclk low to data-out invalid 5?ns note: 1.the falling edge of s6 triggers both the negation of the strobes (asb and dsb) and the falling edge of testclk. either of these events can occur ?st, depending upon the loading on each signal. speci?aton #49 indicates the absolute maximum skew that will occur between the rising edge of the strobes and the falling edge of testclk. figure 7-4. scm68000 to external peripherals timing diagram s0 s1 s2 s3 s4 w w wwwwwwwwww s5s6 s7 s0 a31?0 clki asb rwb data out data in 23 18 41 20 42 51 47 50 42 41 12 49 18 44 45 41 54 29 27 45 testclk avecb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical characteristics motorola ec000 core processor user? manual 7-7 7.8 ac electrical specifications?us arbitration (frequency = 0 to 20 mhz; gnd = 0 vdc, t a = t l to t h ; see figure 7-5 through figure 7-8) num characteristic 3.3 v 5.0 v unit min max min max 7 clock high to address, data bus high impedance (maximum) 25 20 ns 33 clock high to bgb asserted 0 25 0 25 ns 34 clock high to bgb negated 0 25 0 25 ns 35 brb asserted to bgb asserted 1.5 3.5 1.5 3.5 clks 36 1 brb negated to bgb negated 1.5 3.5 1.5 3.5 clks 37 bgackb asserted to bgb negated 1.5 3.5 1.5 3.5 clks 37a 2,4 bgackb asserted to brb negated 10 ns 1.5 clks 10 ns 1.5 clks 38 bgb asserted to control, address, data bus high impedance (asb negated) ?2?2ns 39 bgb width negated 1.5 1.5 clks 46 bgackb width low 1.5 1.5 clks 47 asynchronous input setup time 5?ns 57 bgackb negated to asb, dsb, rwb driven 1.5 1.5 clks 57a bgackb negated to fc driven 1? clks 58 3 brb negated to asb , dsb, rwb driven 1.5 1.5 clks 58a 3 brb negated to fc driven 1? clks notes: 1.setup time for the synchronous inputs bgackb , iplb2 iplb0 , and avecb guarantees their recognition at the next falling edge of the clock. 2.brb need fall at this time only in order to insure being recognized at the end of the bus cycle. 3.the processor will negate bg and begin driving the bus again if external arbitration logic negates br before asserting bgackb. 4.the minimum value must be met to guarantee proper operation. if the maximum value is exceeded, bg may be reasserted. figure 7-5. bus arbitration timing diagram 37a 37 46 36 39 34 38 33 35 clki note: setup time to the clock (#47) for the asynchronous inputs berrb, bgackb, brb, dtackb, iplb2?plb0, and avecb guarantees their recognition at the next falling edge of the clock. brb bgackb bgb and rwb strobes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical characteristics 7-8 ec000 core processor user? manual motorola figure 7-6. bus arbitration timing diagram?dle bus case clki 47 33 35 34 47 47 46 37 57 38 brb bgb bgackb asb dsb rwb fc2?c0 a31?0 d15?0 note: waveform measurements for all inputs and outputs are specified at: logic high = 0.8 v dd , logic low = 0.2 v dd . 7 37a 57a 58a 58 36 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical characteristics motorola ec000 core processor user? manual 7-9 figure 7-7. bus arbitration timing diagram?ctive bus case clki 47 33 35 34 37a 47 47 46 37 36 57 16 57a brb bgb bgackb asb dsb rwb fc2?c0 a31?0 d15?0 note: waveform measurements for all inputs and outputs are specified at: logic high = 0.8 v dd , logic low = 0.2 v dd . 38 7 58a 58 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical characteristics 7-10 ec000 core processor user? manual motorola figure 7-8. bus arbitration timing diagram?ultiple bus request clki 33 35 37 57a brb bgb bgackb asb dsb rwb fc2?c0 a31?0 d15?0 47 39 39 46 37 46 38 36 58 note: waveform measurements for all inputs and outputs are specified at: logic high = 0.8 v dd , logic low = 0.2 v dd . 58a 37a 57 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical characteristics motorola ec000 core processor user? manual 7-11 7.9 ac electrical specifications?ore applications signals (frequency = 0 to 20 mhz; gnd = 0 vdc; t a = t l to t h ; refer to figure 7-9) num characteristic 3.3 v 5.0 v unit min max min max 6 clock low to siz1?iz0 asserted 20 18 ns 17 asb, dsb negated to erwb high 15 15 ns 18 clock high to erwb high 0 20 0 18 ns c3 clock low to erwb low ?0 18 clks c4 clock low to rmcb asserted ?0 18 clks c5 clock low to rmcb negated ?0 18 ns c7 clock low to tscae asserted ?0 18 ns c8 clock high to stop asserted ?0 18 ns c9 clock low to ipendb asserted ?0 18 ns c10 clock low to refillb asserted ?0 18 ns c11 clock low to statusb asserted ?0 18 ns c12 stop pulse width ? 2 clks c14 refillb pulse width ? 1 clks c15 statusb pulse width 1313 clks c16 clki to clko ??ns c17 1 clock to aoeb, coeb, and doeb asserted 20 18 ns note: 1.aoeb, coeb, and doeb will be a logic high only to put the appropriate signals into a high-impedance state. see section 2 signal description for more information about these signals. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical characteristics 7-12 ec000 core processor user? manual motorola figure 7-9. core application signals timing diagram s0 clki siz1?iz0 a31?0 asb ldsb/udsb rwb erwb rmcb stop ipendb refillb statusb 17 18 c3 c4 s1 s2 s3 s4 s5 s6 s7 c7 c8 c12 tscae c10 c14 c17 c11 c15 c9 6 c16 c5 clko aoeb coeb doeb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola ec000 core processor user? manual index-1 index numerics 16-bit mode 3-1, 3-2 2-wire bus arbitration 3-22 3-wire bus arbitration 3-22 8-bit mode 3-1 a address error exception 4-13, 4-14, 4-22, 4-23 address error vector 4-24 address registers 1-8, 1-10 assertion 2-1, 3-1 asynchronous signals 3-35 automatic vector 4-19 autovectored interrupt 4-7 autovectored interrupt acknowledge cycle 4- 7 b base address registers 1-8 bus arbitration timing diagram?ultiple bus request 7-10 bus cycle 4-14 bus cycle termination 3-42 bus error 3-32, 3-35, 4-20, 4-23 bus error exception 3-30, 3-35, 4-13, 4-14, 4- 22 bus error exception vector 3-30 bus error termination 3-42 bus error vector 4-22 c condition code register 1-8 condition codes 1-8 core application signals timing diagram 7-12 d data bus 3-15 data registers 1-8, 1-10 data types 1-11 debugging 4-22 design flow 1-5 double bus fault 3-35 e ec000 core 1-1, 2-1, 3-1, 4-1, 7-1 exception 4-13, 4-15, 4-21 exception handler 4-14 exception processing 3-30, 4-2, 4-13, 4-14, 4- 19, 4-21, 4-22, 4-24 exception processing state 4-1 exception stack frame 4-14, 4-15, 4-21 exception type 4-11 exception vector 4-11, 4-15, 4-21, 4-23 external exception 4-13 f features of the scm68000 1-1 flexcore program 1-1 g general-purpose registers 1-8 h halt operation 3-32 halt termination 3-42 halt/run/single-step operation 3-32 halted processing state 4-1 handler routine 4-11, 4-14, 4-23 i illegal instruction exception 4-21 illegal instruction trap 4-21 illegal instruction vector 4-21 instructions andi to sr 4-2 chk 4-13, 4-21 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
index index-2 ec000 core processor user? manual motorola div 4-13 divs 4-21 divu 4-21 eori to sr 4-2 illegal 4-21, 4-22 jmp 5-7, 6-7 jsr 5-7, 6-7 lea 5-7, 6-7 move to sr 4-2 movem 5-7, 6-7 pea 5-7, 6-7 reset 4-2, 4-16 rte 4-2 stop 4-1, 4-2 tas 3-13 trap 4-13, 4-21, 4-22 trapv 4-13, 4-21 internal exception 4-13 interrupt 4-13 interrupt acknowledge cycle 2-8, 3-2, 4-3, 4- 14, 4-19 interrupt exception 4-13, 4-14, 4-22 interrupt mask 1-8 interrupt mask level 4-16 interrupt priority 4-19 interrupt priority mask 4-1, 4-15 interrupt request 4-19 interrupt vector number 4-20 m mdadecal 1-5 n negation 2-1, 3-1 nonmaskable interrupt 4-20 normal processing state 4-1 normal termination 3-42 notational conventions 1-11 p pending interrupt 4-19 privilege mode 4-19 privilege violation vector 4-22 program counter 1-8, 3-30, 4-14, 4-15, 4-16, 4- 19, 4-22, 4-23 pseudo-asynchronous 3-37 r read and write bus cycle states 3-39 read cycle 3-37, 5-1, 6-1 read cycle states 3-6 read-modify-write cycle 3-30, 3-32 read-modify-write cycle states 3-14 reset 4-23 reset exception 4-13, 4-14, 4-16, 4-22 reset exception vector 4-15 reset operation 3-35 reset vector table entry 4-16 retry operation 3-32, 3-35 retry termination 3-42 s s-bit 4-2, 4-14 scm68000 1-1, 2-1, 3-1, 4-1, 7-1 signal names address bus 2-1, 3-6, 3-11, 3-14, 3-15 address output enable 2-8 address strobe 2-3, 3-30, 3-32, 3-43 address three-state control 2-9 autovector 2-8 bus error 2-6, 3-30 bus grant 2-5, 3-17 bus grant acknowledge 2-5, 3-17 bus request 2-5, 3-17, 3-19 clock 2-1 control output enable 2-8 cpu pipe refill 2-9 data bus 2-1, 3-7, 3-12, 3-32 data output enable 2-8 data strobe 2-4 data transfer acknowledge 2-4 data transfer size 2-4 disable control 2-7 early read/write 2-3 function codes 2-8, 3-32 halt 2-6 interrupt control 2-5 interrupt pending 2-9 lower data strobe 2-4 microsequencer status indication 2-9 mode 2-7 read/write 2-3 read-modify-write 2-5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
index motorola ec000 core processor user? manual index-3 reset 2-6 stop instruction indicator 2-9 test clock 2-7 test mode 2-7 upper data strobe 2-4 signals a0 3-2 a1 3-2 a31?0 2-1 aoeb 2-8 asb 2-3, 3-7, 3-12, 3-13, 3-15, 3-16, 3-17, 3-18, 3-19, 3-36, 3-37, 3-40, 3-41 avecb 2-8, 3-35, 3-36, 4-7, 4-20 berrb 2-6, 3-7, 3-12, 3-15, 3-16, 3-30, 3- 32, 3-35, 3-36, 3-41, 3-42, 3-43, 4-20 bgackb 2-5, 3-17, 3-18, 3-19, 3-35 bgb 2-5, 3-18, 3-19 brb 2-5, 3-18, 3-35 clki 2-1, 5-1, 6-1 clko 2-1 coeb 2-8 d15?0 2-1 disb 2-7 doeb 2-8 dsb 2-4, 3-7, 3-12, 3-15, 3-16, 3-17, 3-36, 3-40, 3-41 dtackb 2-4, 3-7, 3-12, 3-15, 3-16, 3-19, 3- 30, 3-35, 3-36, 3-37, 3-38, 3-41, 3- 42, 3-43, 4-3, 4-7, 4-20 erwb 2-3, 3-11, 3-13, 3-14, 3-15, 3-16, 3- 39, 3-41 fc2?c0 2-8, 3-6, 3-11, 3-14, 3-15 haltib 2-6, 3-30, 3-32, 3-35, 3-36, 3-42, 3- 43, 4-18 haltob 2-6, 3-35 ipendb 2-9 iplb2?plb0 2-5, 3-35, 4-19, 4-20 ldsb 2-4, 3-1, 3-2, 3-7, 3-12, 3-15, 3-16, 3- 17, 3-36, 3-40, 3-41 mode 2-7, 3-1 refillb 2-9 resetib 2-6, 3-35, 3-41, 4-16 resetob 2-6, 4-16 rmcb 2-5 rwb 2-3, 3-6, 3-11, 3-12, 3-14, 3-15, 3-16, 3-37, 3-39, 3-41 siz1?iz0 2-4 statusb 2-9 stop 2-9 test 2-7, 4-18 testclk 2-7, 4-7 tscae 2-9, 3-6, 3-7, 3-11, 3-14, 3-40 udsb 2-4, 3-1, 3-2, 3-7, 3-12, 3-15, 3-16, 3- 17, 3-36, 3-40, 3-41 single-step mode 3-32 software stack pointers 1-8 spurious interrupt vector 4-19 sr 1-8 ssp 1-8, 4-2, 4-15, 4-16 stack pointer 1-10 standard cell 1-5 status register 1-8, 3-30, 4-2, 4-11, 4-14, 4-16, 4-19, 4-21, 4-22 stopped state 4-1 supervisor data space 4-11 supervisor mode 1-7, 1-8, 4-1, 4-2, 4-14, 4-19, 4-22 supervisor program space 4-15 supervisor references 4-2 supervisor stack 4-14 supervisor stack pointer 1-8, 4-1 supervisor state 4-15, 4-16 supervisor/user bit 4-1 synchronization 3-42 t t-bit 4-14, 4-22 termination of a bus cycle 3-42 test and set instruction 3-13 trace enable bit 4-1 trace exception 4-22 trace exception vector 4-22 trace state 4-15 tracing 4-14, 4-16, 4-19, 4-22 trap 4-21 trap exception 4-22 u unimplemented instruction 4-21 uninitialized interrupt vector number 4-20 user interrupt vectors 4-11 user mode 1-7, 1-8, 4-1, 4-2, 4-21 user references 4-2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
index index-4 ec000 core processor user? manual motorola user stack pointer 1-8, 4-1 usp 1-8, 4-2 v vector address 4-11 vector number 4-11, 4-14, 4-15, 4-19, 4-21, 4- 22, 4-24 vector table 4-11 verilog 1-5 veritime 1-5 w write cycle 3-37, 5-1, 6-1 write cycle states 3-11 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

▲Up To Search▲

Price & Availability of MC68EC000

	To Download MC68EC000 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .